Thermal Fatigue Analysis of PBGA Solder Joints With the Consideration of Damage Evolution

2000 ◽  
Author(s):  
Shi-Wei Ricky Lee ◽  
Keith Newman ◽  
Livia Hu

Abstract This paper presents a computational thermal fatigue analysis for the life prediction of solder joints in a plastic ball grid array-printed circuit board (PBGA-PCB) assembly. The PBGA has a full grid array of 256 solder balls with 1.0 mm ball pitch. The PCB is a 4-layer FR-4 laminate with a thickness of 1.57 mm (62 mils). The assembly is subjected to −40∼125°C thermal cycling (one-hour cycle). Finite element analysis is performed to obtain the creep hysteresis loops. Based on a previously developed model, the evolution of damage is considered in the life prediction of solder joints. Besides, PCBs with various thicknesses (40 mils and 20 mils) are investigated. The results from different cases are compared and discussed.

Author(s):  
Minoru Mukai ◽  
Kenji Hirohata ◽  
Hiroyuki Takahashi ◽  
Takashi Kawakami ◽  
Kuniaki Takahashi

Fatigue life prediction of solder joints is one of the most important areas of research in the development of reliable electronic packages. Recent trends in electronic package development indicate a shift toward smaller solder joints and larger package sizes, and temperature changes under field conditions are also becoming greater. Since reliability design of solder joints has become severer, the estimation of the crack propagation is becoming important like the estimation of the crack initiation. In the present study, a new method of estimating the crack propagation, which is based on finite element analysis without geometrical crack model, was examined, in order to ensure suitability for practical use in electronic package design. On the basis of a damage model assumed for Sn-37Pb solder, the new method called ‘damage path simulation’ was verified for solder joints in QFP (Quad Flat Package). In the case of solder joints of the gull-wing type, fatigue cracks are commonly initiated from the upper surface of the solder fillet, and propagated in the vicinity of the interface with the outer lead. It was clear that the extension of the damage path showed good agreement with the behavior of crack propagation observed in the actual thermal cycle tests. Damage path extension from a pointed end of outer lead is also simulated simultaneously with that from the upper surface of the solder fillet, and both damage paths were finally combined at a gap between outer lead and printed circuit board. The advantage of the present method is especially evident when the fatigue cracks were initiated from two or more regions. From the results of this study, it was concluded that the estimation of the crack propagation in solder joints based on the present method is satisfactory for engineering purposes.


2010 ◽  
Vol 118-120 ◽  
pp. 738-742
Author(s):  
Xue Xia Yang ◽  
Yu Zhang ◽  
Xue Feng Shu

The purpose of this paper is to study the ability of solder joints to resist thermal fatigue. 2D simplified models of Plastic Ball Grid Array package (PBGA) structures with ten different solder joints obtained from surface mount experiment are established by finite element software, then stress-strain response of solder joints subjected to the thermal cycle load are calculated. And the effects of shape parameters of solder joints on the ability to resist thermal fatigue are discussed. Results indicate that for the same material and volume solders, the solder joints which have higher height, smaller diameter and contact angle have a stronger ability against thermal fatigue, and that the thermal fatigue characteristics are also greatly influenced by the solder outlines. Comparing with SP solder joints, LF solder joints have stronger ability against thermal fatigue.


2006 ◽  
Vol 128 (4) ◽  
pp. 441-448 ◽  
Author(s):  
S. Chaparala ◽  
J. M. Pitarresi ◽  
S. Parupalli ◽  
S. Mandepudi ◽  
M. Meilunas

One of the primary advantages of surface mount technology (SMT) over through-hole technology is that SMT allows the assembly of components on both sides of the printed circuit board (PCB). Currently, area array components such as ball grid array (BGA) and chip-scale package (CSP) assemblies are being used in double-sided configurations for network and memory device applications as they reduce the routing space and improve electrical performance (Shiah, A. C., and Zhou, X., 2002, “A Low Cost Reliability Assessment for Double-Sided Mirror-Imaged Flip Chip BGA Assemblies,” Proceedings of the Seventh Annual Pan Pacific Microelectronics Symposium, Maui, Hawaii, pp. 7–15, and Xie, D., and Yi, S., 2001, “Reliability Design and Experimental work for Mirror Image CSP Assembly”, Proceedings of the International Symposium on Microelectronics, Baltimore, October, pp. 417–422). These assemblies typically use a “mirror image” configuration wherein the components are placed on either side of the PCB directly over each other; however, other configurations are possible. Double-sided assemblies pose challenges for thermal dissipation, inspection, rework, and thermal cycling reliability. The scope of this paper is the study of the reliability of double-sided assemblies both experimentally and through numerical simulation. The assemblies studied include single-sided, mirror-imaged, 50% offset CSP assemblies, CSPs with capacitors on the backside, single-sided, mirror-imaged plastic ball grid arrays (PBGAs), quad flat pack (QFP)/BGA mixed assemblies. The effect of assembly stiffness on thermal cycling reliability was investigated. To assess the assembly flexural stiffness and its effect on the thermal cycling reliability, a three-point bending measurement was performed. Accelerated thermal cycling cycles to failure were documented for all assemblies and the data were used to calculate the characteristic life. In general, a 2X to 3X decrease in reliability was observed for mirror-image assemblies when compared to single-sided assemblies for both BGAs and CSPs on 62mil test boards. The reliability of mirror-image assemblies when one component was an area array device and the other was a QFP was comparable to the reliability of the single-sided area array assemblies alone, that is, the QFP had almost no influence on the double-sided reliability when used with an area array component. Moiré interferometry was used to study the displacement distribution in the solder joints at specific locations in the packages. Data from the reliability and moiré measurements were correlated with predictions generated from three-dimensional finite element models of the assemblies. The models incorporated nonlinear and time-temperature dependent solder material properties and they were used to estimate the fatigue life of the solder joints and to obtain an estimate of the overall package reliability using Darveaux’s crack propagation method.


1994 ◽  
Vol 116 (2) ◽  
pp. 83-88 ◽  
Author(s):  
R. K. Govila ◽  
E. Jih ◽  
Y.-H. Pao ◽  
C. Larner

Leadless chip resistors (LCR) made by two different manufacturers and surface mounted on glass/epoxy printed circuit board (PCB) were subjected to thermal cycling between −55°C to 125°C in order to induce thermal fatigue failure/damage. The test units were subjected to a maximum of 250 thermal cycles. Solder joints in both types of LCRs were examined in scanning electron microscope and a relative comparison of the extent of fatigue damage is presented. The failure mechanism is associated with cracking in the eutectic compostion Sn/Pb solder initiated at the stress concentration sites. A nonlinear, time-dependent finite element modeling analysis has been performed to determine critical stress concentration sites in the solder joint. Key parameters leading to the initiation of solder damage are identified, and recommendations are made to improve the design in terms of solder configuration such as the radius of corner of the alumina substrate and the standoff height.


2010 ◽  
Vol 34-35 ◽  
pp. 451-455
Author(s):  
Fang Liu ◽  
Guang Meng

Finite element (FE) method is an efficient and power tool, and is adopted to analyze dynamic response of printed circuit board (PCB) assembly. First, FE model of PCB assembly was established. Second, the dynamic behaviors of ball gird array (BGA) lead-free solder joint were obtained when the PCB assembly was subjected to a half-sine acceleration pulse. Results show that the maximum tensile stresses occur at solder joints located at the four outermost corners of BGA and solder joints at outermost corners are the most vulnerable to crack. In addition, it can be found during FE analysis that the solder joint reliability can be enhanced as the PCB damping increases and input acceleration level reduces.


Materials ◽  
2019 ◽  
Vol 12 (6) ◽  
pp. 960 ◽  
Author(s):  
Min-Soo Kang ◽  
Do-Seok Kim ◽  
Young-Eui Shin

To analyze the reinforcement effect of adding polymer to solder paste, epoxies were mixed with two currently available Sn-3.0Ag-0.5Cu (wt.% SAC305) and Sn-59Bi (wt.%) solder pastes and specimens prepared by bonding chip resistors to a printed circuit board. The effect of repetitive thermal stress on the solder joints was then analyzed experimentally using thermal shock testing (−40 °C to 125 °C) over 2000 cycles. The viscoplastic stress–strain curves generated in the solder were simulated using finite element analysis, and the hysteresis loop was calculated. The growth and propagation of cracks in the solder were also predicted using strain energy formulas. It was confirmed that the epoxy paste dispersed the stress inside the solder joint by externally supporting the solder fillet, and crack formation was suppressed, improving the lifetime of the solder joint.


Author(s):  
Takahiro Omori ◽  
Kenji Hirohata ◽  
Tomoko Monda ◽  
Minoru Mukai

There is high demand for fatigue life prediction of solder joints in electronic packages such as ball grid arrays (BGAs). A key component of fatigue life prediction technology is a canary device, which warns of the impending risk of failure through loss of function before other important parts become severely impaired. In a BGA package, thermal fatigue of solder joints normally starts from the solder joints at the outermost part of the package. This can be taken advantage of by using the outermost solder joints as canary devices for detecting the degree of cumulative mechanical fatigue damage. To accurately estimate the lifetimes of other functional solder joints, it is essential to understand the relationship between the fatigue lives of canary joints and other functional joints. Damage path simulation is therefore proposed for predicting the crack propagation in solder joints on electronic packages through numerical simulation. During the process of designing the layout of canary joints and other joints, it is very useful to know not only the relationship between the fatigue lives of the canary and other joints, but also the path of crack propagation through all joints. This paper presents a method for estimating the relationship between the fatigue lives of canary joints and other joints by using damage path simulation. Some BGA packages mounted on a printed circuit board are modeled to demonstrate the process of estimating the lifetime of each joint under thermal cycle loading. A large-scale finite element model is used to accurately represent the geometrical properties of the printed circuit board and package. Both crack initiation and crack propagation processes can be simultaneously evaluated by modeling all of the solder joints on each package. The results show that damage path simulation and large-scale modeling are useful for determining the layout of canary joints in electronic packages.


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