A Joint-Coding Scheme With Crosstalk Avoidance

2011 ◽  
Author(s):  
Lei Zhou ◽  
Ning Wu ◽  
Fen Ge
Keyword(s):  
Error Detection ◽  
Error Control ◽  
Fault Tolerant ◽  
Experimental Result ◽  
Error Control Coding ◽  
Coding Scheme ◽  
Decode Scheme ◽  
On Chip ◽  
Joint Coding ◽  
Crosstalk Avoidance

The reliable transfer in Network on Chip can be guaranteed by crosstalk avoidance and error detection code. In this paper, we propose a joint coding scheme combined with crosstalk avoidance coding with error control coding. The Fibonacci numeral system is applied to satisfy the requirement of crosstalk avoidance coding, and the error detection is achieved by adding parity bits. We also implement the codec in register transfer level. Furthermore, the schemes of codec applying to fault-tolerant router are analyzed. The experimental result shows that “once encode, multiple decode” scheme outperforms other schemes in trade-off of delay, area and power.

scholarly journals Adaptive Multibit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication

2016 ◽  
Vol 63 (2) ◽  
pp. 166-170 ◽  
Author(s):  
Wameedh Nazar Flayyih ◽  
Khairulmizam Samsudin ◽  
Shaiful Jahari Hashim ◽  
Yehea I. Ismail ◽  
Fakhrul Zaman Rokhani
Keyword(s):  
Error Control ◽  
Error Control Coding ◽  
Coding Scheme ◽  
On Chip

Design of Self-Tuning Fuzzy Control and Fault Tolerant Error Control Coding Based on Graphic User Interface for Smart Hybrid Powerpack

2014 ◽  
Vol 574 ◽  
pp. 528-533
Author(s):  
Jek Wang Choi ◽  
Lei Lei Shi ◽  
Li Jun Wu ◽  
Hyeon Woo Kim ◽  
Iksu Choi ◽  
...  
Keyword(s):  
User Interface ◽  
Fuzzy Control ◽  
Intelligent Control ◽  
High Speed ◽  
Error Control ◽  
Fault Tolerant ◽  
Graphic User Interface ◽  
Error Control Coding ◽  
Self Tuning ◽  
Network Fault

The Smart Hybrid Powerpack (SHP) is an electro-hydraulic system which combines the system of Electro Hydraulic Actuator (EHA) and advanced technologies such as network fault tolerance and intelligent control. EHA system has been famous in the industry because that the EHA acts as a power-shift which shifts the power from high-speed electric motor to the high-force of hydraulic cylinder by bi-directional piston pump. If errors in the plant and network occur in the SHP, the system will cause serious malfunctions. To reduce plant noises and network errors, this paper shows the intelligent control method comparing Self-tuning fuzzy with fuzzy control and network fault tolerant error control coding in the SHP. In the intelligent control part, the simulation result shows good performance to reduce plant noises by the self-tuning fuzzy than fuzzy control. In the network fault tolerant error control coding part, proposed scheme also shows good performance by CRC code and Reed-Solomon (R-S) code in two channel (CRT) method than one channel only. We developed LabVIEW Graphic User Interface (GUI) to show these simulation results. Using this GUI, we can save time to experiment and get benefit of guidance to make real program.

scholarly journals Fuzzy Based Adaptive Controller for on - Chip Communication

2018 ◽  
Vol 7 (3.27) ◽  
pp. 362
Author(s):  
M Jasmin ◽  
T Vigneswaran
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Error Detection ◽  
Input Data ◽  
Fuzzy Controller ◽  
Proper Time ◽  
System On Chip ◽  
Coding Scheme ◽  
Error Detection And Correction ◽  
On Chip

Occurrence of bit error is more when communication takes place in System on chip environment. By employing proper error detection and correction codes the bit error rate can be considerably reduced in On-chip communication. As System on chip involves heterogeneous system the efficiency of communication is improved when reconfigurable multiple coding schemes are preferred. Depending upon the requirements for various subsystem the correct code has to be selected. Due to the variations in input demands based on various subsystems the proper selection of codes become fuzzy in nature. In this paper Fuzzy Controller is designed to select the correct coding scheme. Inputs are given to the fuzzy controller based on the application demand of the user. The input parameters are minimum bit error rate, computational complexity and correlation level of the input data. Fuzzy Controller employs three membership functions and 27 rules to select the appropriate coding scheme. The selected coding scheme should be communicated at the proper time to the decoder. To enable the decoding process selected coding scheme is communicated effectively by using less overhead frame format. To verify the functionality of fuzzy controller random input data sets are used for testing.  

Hamming Product Code Based Multiple Bit Error Correction Coding Scheme Using Keyboard Scan Based Decoding for on Chip Interconnects Links

2012 ◽  
Vol 241-244 ◽  
pp. 2457-2461 ◽  
Author(s):  
Murali Maheswari ◽  
Gopalakrishnan Seetharaman
Keyword(s):  
Error Correction ◽  
Error Rate ◽  
Iterative Decoding ◽  
Error Control ◽  
Low Complexity ◽  
Hardware Complexity ◽  
Error Correction Coding ◽  
Product Code ◽  
Coding Scheme ◽  
On Chip

In this paper, we present multiple bit error correction coding scheme using extended Hamming product code combined with type II HARQ and keyboard scan based error flipping to correct multiple bit errors for on chip interconnect. The keyboard scan based error flipping reduces the hardware complexity of the decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 86% of reduction in area and 23% of reduction in decoder delay with only small increase in residual flit error rate compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 66% of links power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links.

A Concatenate Code for Error Correcting Code in Bit Pattern Media Recoding System

2013 ◽  
Vol 834-836 ◽  
pp. 962-967 ◽  
Author(s):  
Sekson Timakul ◽  
Santi Koonkarnkhai ◽  
Piya Kovintavewat ◽  
Somsak Choomchuay
Keyword(s):  
Error Control ◽  
Error Correcting Code ◽  
Ldpc Code ◽  
Areal Density ◽  
Conventional Technique ◽  
Concatenated Coding ◽  
Error Control Coding ◽  
Outer Code ◽  
Rs Codes ◽  
Coding Scheme

Bit Pattern Media Recording (BPMR) is the modern HDD recording technique which can overcome the constraint of conventional technique by offering tremendous areal density. However, narrow track of BPMR can cause noise generating from inter-track interference (ITI) and In. inter-symbol interference (ISI). One traditional technique used to improve BER of the system is the introducing of error control coding. In this paper, we investigate concatenate code applied to BPMR. We proposed inner code with low-density parity-check (LDPC) and Reed-Solomon (RS) codes as outer code. The obtained simulation results confirmed to us that the concatenated coding scheme yielded better performance compared with the single LDPC code deployment.

scholarly journals Analysis Of The Effectiveness Of Error Detection In Data Transmission Using Polynomial Code Method

2011 ◽  
Vol 14 (2) ◽  
Author(s):  
Daniel N. Owunwanne
Keyword(s):  
Error Detection ◽  
Data Transmission ◽  
Error Control ◽  
Data Transfer ◽  
Detection Methods ◽  
Error Control Coding ◽  
Transfer Rates ◽  
Free Data ◽  
Ethernet Network ◽  
Corrective Method

Data transmitted from one location to the other has to be transferred reliably. Usually, error control coding algorithm provides the means to protect data from errors. Unfortunately, in many cases the physical link can not guarantee that all bits will be transferred without errors. It is then the responsibility of the error control algorithm to detect those errors and in some cases correct them so that upper layers will receive error free data. The polynomial code, also known as Cyclic Redundancy Code (CRC) is a very powerful and easily implemented technique to obtain data reliability. As data transfer rates and the amount of data stored increase, the need for simple and robust error detection codes should increase as well. Thus, it is important to be sure that the CRCs in use are as effective as possible. Unfortunately, standardized CRC polynomials such as the CRC-32 polynomial used in the Ethernet network standard are known to be grossly suboptimal for important applications, (Koopman, 2002). This research investigates the effectiveness of error detection methods in data transmission used several years ago when we had to do with small amount of data transfer and data storages compared with the huge amount of data we deal with nowadays.  A demonstration of erroneous bits in data frames that may not be detected by the CRC method will be shown. A corrective method to detect errors when dealing with humongous data transmission will also be given.

scholarly journals A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture

2011 ◽  
Vol 2011 ◽  
pp. 1-15 ◽  
Author(s):  
Mohsin Amin ◽  
Abbas Ramazani ◽  
Fabrice Monteiro ◽  
Camille Diou ◽  
Abbas Dandache
Keyword(s):  
Fault Tolerance ◽  
Error Detection ◽  
Error Control ◽  
Fault Tolerant ◽  
Error Rates ◽  
Main Memory ◽  
Transient Faults ◽  
Processor Core ◽  
Detection Techniques ◽  
Performance Area

We introduce a specialized self-checking hardware journal being used as a centerpiece in our design strategy to build a processor tolerant to transient faults. Fault tolerance here relies on the use of error detection techniques in the processor core together with journalization and rollback execution to recover from erroneous situations. Effective rollback recovery is possible thanks to using a hardware journal and chosing a stack computing architecture for the processor core instead of the usual RISC or CISC. The main objective of the journalization and the hardware self-checking journal is to prevent data not yet validated to be sent to the main memory, and allow to fast rollback execution on faulty situations. The main memory, supposed to be fault secure in our model, only contains valid (uncorrupted) data obtained from fault-free computations. Error control coding techniques are used both in the processor core to detect errors and in the HW journal to protect the temporarily stored data from possible changes induced by transient faults. Implementation results on an FPGA of the Altera Stratix-II family show clearly the relevance of the approach, both in terms of performance/area tradeoff and fault tolerance effectiveness, even for high error rates.

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