Assessment of Fatigue Induced Pad Cratering With a Universal Expression of Printed Circuit Board Fatigue Resistance

2020 ◽  
Vol 142 (2) ◽  
Author(s):  
Qiming Zhang ◽  
S. W. Ricky Lee
Keyword(s):  
Printed Circuit Board ◽  
Drop Test ◽  
Circuit Board ◽  
Bending Test ◽  
Cyclic Bending ◽  
Pcb Assembly ◽  
Testing Method ◽  
Pad Cratering ◽  
Drop Tests ◽  
Board Level

Abstract Repeated loading is an important reason to cause pad cratering fatigue failure in ball grid array (BGA) device in printed circuit board (PCB) assembly. For industry application, the board level drop test is commonly applied to evaluate the pad cratering fatigue strength under the repetitive drop loading. Although this testing method is consistent with the actual service condition of BGA-PCB assembly, it is extremely time consuming in the testing operation and expensive in costs. Another fatigue evaluation testing method for BGA-PCB assembly is the board level cyclic bending test. Compare with the board level drop test, this testing method can be handled by universal testing machine automatically without manual operation during the testing process. In consequence, the cyclic bending test has the merits of simple, fast, and low costs, and it is always desirable to evaluate the repeated drop life of pad cratering with cyclic bending test. This research proposes a correlation between the cyclic bending and repetitive drop test in BGA-PCB assemblies. With assistance of finite element method, the equivalent cyclic bending testing conditions of drop tests are developed. The experimental validation is also conducted to prove accuracy of the correlation. From the analysis of finite element method and experiments, both cyclic bending tests and repetitive drop tests agree with the same strain–number of cycle (S–N) curve. This means the S–N curve can be treated as a generalized failure criterion of fatigue induced pad cratering. The conclusion is crucial for reliability design phases to prevent the pad cratering fatigue failure.

Numerical Model to Simulate the Drop Test of Printed Circuit Board (PCB)

2011 ◽  
Vol 423 ◽  
pp. 26-30
Author(s):  
S. Assif ◽  
M. Agouzoul ◽  
A. El Hami ◽  
O. Bendaou ◽  
Y. Gbati
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Drop Test ◽  
Dynamic Responses ◽  
Circuit Board ◽  
Joint Stress ◽  
Printed Circuit ◽  
Increasing Demand ◽  
Improved Model ◽  
Board Level

Increasing demand for smaller consumer electronic devices with multi-function capabilities has driven the packaging architectures trends for the finer-pitch interconnects, thus increasing chances of their failures. A simulation of the Board Level Drop-Test according to JEDEC (Joint Electron Device Council) is performed to evaluate the solder joint reliability under drop impact test. After good insights to the physics of the problem, the results of the numerical analysis on a simple Euler-Bernoulli beam were validated against analytical analysis. Since the simulation has to be performed on ANSYS Mechanical which is an implicit software, two methods were proposed, the acceleration-input and the displacement-input. The results are the same for both methods. Therefore, the simulation is carried on the real standard model construction of the board package level2. Then a new improved model is proposed to satisfy shape regular element and accuracy. All the models are validated to show excellent first level correlation on the dynamic responses of Printed Circuit Board, and second level correlation on solder joint stress. Then a static model useful for quick design analysis and optimization’s works is proposed and validated. Finally, plasticity behavior is introduced on the solder ball and a non-linear analysis is performed.

Failure Analysis of Halogen-Free Printed Circuit Board Assembly Under Board-Level Drop Test

2012 ◽  
Vol 134 (1) ◽  
Author(s):  
Hung-Jen Chang ◽  
Chau-Jie Zhan ◽  
Tao-Chih Chang ◽  
Jung-Hua Chou
Keyword(s):  
Printed Circuit Board ◽  
Drop Test ◽  
Circuit Board ◽  
Printed Circuit Board Assembly ◽  
Printed Circuit ◽  
Plastic Ball ◽  
Circuit Board Assembly ◽  
Halogen Free ◽  
Board Level ◽  
The Impact

In this study, a lead-free dummy plastic ball grid array component with daisy-chains and Sn4.0Ag0.5Cu Pb-free solder balls was assembled on an halogen-free high density interconnection printed circuit board (PCB) by using Sn1.0Ag0.5Cu solder paste on the Cu pad surfaces of either organic solderable preservative (OSP) or electroless nickel immersion gold (ENIG). The assembly was tested for the effect of the formation extent of Ag3Sn intermetallic compound. Afterward a board-level pulse-controlled drop test was conducted on the as-reflowed assemblies according to the JESD22-B110 and JESD22-B111 standards, the impact performance of various surface finished halogen-free printed circuit board assembly was evaluated. The test results showed that most of the fractures occurred around the pad on the test board first. Then cracks propagated across the outer build-up layer. Finally, the inner copper trace was fractured due to the propagated cracks, resulting in the failure of the PCB side. Interfacial stresses numerically obtained by the transient stress responses supported the test observation as the simulated initial crack position was the same as that observed.

High-Speed Cyclic Bend Tests and Board-Level Drop Tests for Evaluating the Robustness of Solder Joints in Printed Circuit Board Assemblies

2009 ◽  
Vol 38 (6) ◽  
pp. 884-895 ◽  
Author(s):  
E.H. Wong ◽  
S.K.W. Seah ◽  
C.S. Selvanayagam ◽  
R. Rajoo ◽  
W.D. van Driel ◽  
...  
Keyword(s):  
High Speed ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Printed Circuit ◽  
Drop Tests ◽  
Bend Tests ◽  
Board Level

Modeling and Simulation of PCB Assembly under Board-Level Drop Impact

2010 ◽  
Vol 34-35 ◽  
pp. 451-455
Author(s):  
Fang Liu ◽  
Guang Meng
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Fe Model ◽  
Fe Method ◽  
Acceleration Pulse ◽  
Pcb Assembly ◽  
Free Solder ◽  
Board Level

Finite element (FE) method is an efficient and power tool, and is adopted to analyze dynamic response of printed circuit board (PCB) assembly. First, FE model of PCB assembly was established. Second, the dynamic behaviors of ball gird array (BGA) lead-free solder joint were obtained when the PCB assembly was subjected to a half-sine acceleration pulse. Results show that the maximum tensile stresses occur at solder joints located at the four outermost corners of BGA and solder joints at outermost corners are the most vulnerable to crack. In addition, it can be found during FE analysis that the solder joint reliability can be enhanced as the PCB damping increases and input acceleration level reduces.

Understanding and Testing for Drop Impact Failure

2005 ◽  
Author(s):  
S. K. W. Seah ◽  
E. H. Wong ◽  
R. Ranjan ◽  
C. T. Lim ◽  
Y.-W. Mai
Keyword(s):  
Printed Circuit Board ◽  
Mechanical Response ◽  
Solder Joints ◽  
Drop Impact ◽  
Consumer Products ◽  
Circuit Board ◽  
Bga Packages ◽  
Response Board ◽  
Drop Tests ◽  
Board Level

This paper presents the results of experiments aimed at studying the effects of drop impact on portable electronics and reproducing these effects in controllable tests. Firstly, a series of drop tests were performed on consumer products (mobile phones and PDAs) to understand how the printed circuit board (PCB) within a product behaves in actual drop conditions. These product-level drop tests show that in drop impact, there are three possible types of mechanical response which can stress the 2nd level interconnections of CSP and BGA packages, namely: 1) flexing of the PCB on its supports, dominated by the 1st (fundamental) natural frequency; 2) flexing of the PCB resulting from direct impact or knocking against the PCB, typically dominated by higher natural frequencies; and 3) inertia loading on the solder joints due to high accelerations. Next, a series of board-level experiments were designed to separately study each of the three types of mechanical response. Board flexing due to direct impacts is the most severe response due to the strong strain amplitudes generated. Given the same input shock, the conventional board-level test — where the PCB flexes on its supports — produces much lower strain amplitudes. Inertia loading on the solder joints is practically negligible. Since PCB flexing is the main failure driver, a simple vibration test, which reproduces the strains observed in drop impact, is suggested as an alternative to time-consuming drop impact tests.

Viscoelastic Influence on Dynamic Properties of PCB Under Drop Impact

2007 ◽  
Vol 129 (3) ◽  
pp. 266-272 ◽  
Author(s):  
Fang Liu ◽  
Guang Meng ◽  
Mei Zhao
Keyword(s):  
Printed Circuit Board ◽  
Dynamic Properties ◽  
Substrate Material ◽  
Drop Impact ◽  
Circuit Board ◽  
Theoretical Research ◽  
Reliability Design ◽  
Pcb Assembly ◽  
Impact Reliability ◽  
Board Level

Dynamic properties of printed circuit board (PCB) assembly under drop impact are investigated when viscoelasticity of substrate materials is considered. The main materials of a PCB substrate are macromolecule resins, which are typical viscoelastic materials. From the viewpoint of viscoelasticity, the dynamics of PCBs under drop impact is analyzed based on mass-damping-spring, beam, and plate theories. It is demonstrated that the viscoelasticity of a PCB has distinct influences on the dynamic properties of PCBs under board-level drop impact. When there is an increase in the viscosity of substrate materials, the damping coefficients of PCBs would rise, its deflection and acceleration responses could diminish faster, and the maximum deflection of PCBs would become smaller. Meanwhile, with the same viscosity and drop impact conditions, a larger plate would produce a bigger deflection response. Therefore, drop impact reliability could be enhanced by choosing substrate material of larger viscoelasticity and reducing properly the size of PCBs. Dynamic analysis of PCBs under drop impact not only contributes to perfecting theoretical research, but also provides a reference for the choice of substrate materials and reliability design of PCBs when electronic products are devised.

Board Level Drop Test Analysis Based on Modal Test and Simulation

2008 ◽  
Vol 130 (2) ◽  
Author(s):  
Fang Liu ◽  
Guang Meng ◽  
Mei Zhao ◽  
Junfeng Zhao
Keyword(s):  
Elastic Modulus ◽  
Dynamic Simulation ◽  
Printed Circuit Board ◽  
Digital Camera ◽  
Simulation Method ◽  
Drop Test ◽  
Circuit Board ◽  
Test Analysis ◽  
Test Board ◽  
Board Level

Solder joint reliability in drop test is crucial for handheld systems, such as mobile phone, digital camera, and MP3 player. In recent years, a lot of experiments and simulations have been carried out by researchers to study board level drop test, and many useful results have been obtained. Regarding mechanical simulation and analysis, there are still two challenges: How to design drop test printed circuit board (PCB) based on dynamic simulation and analysis? How to get accurate elastic modulus of PCB, especially damping parameters, as property inputs for drop test simulation? In this study, an approach based on systematic modal tests and analyses is used to address these two challenges. First, modal dynamic simulation is used to design the test board to meet drop test requirements. Second, modal tests are conducted on drop test board in order to validate dynamic simulation and measure structural damping parameters and overall board elastic modulus as well. Adopted directly in drop test simulation, the measured damping parameters and elastic modulus are proved to be accurate. It is verified through comparison between the finite element simulation and real drop test results. With the modal tests and simulation method established here, drop simulation becomes very simple and accurate, and test board design and characterization are also simplified. Thus, considerable drop test experiment and simulation fine tune, and validation work can be saved.

In-Situ Mechanical Sample Preparation of Selected Sites and Components on Large Modules and Boards

2016 ◽  
Author(s):  
Jim Colvin ◽  
Timothy Hazeldine ◽  
Heenal Patel
Keyword(s):  
Sample Preparation ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Tilt Table ◽  
Standard Requirement ◽  
Open Design ◽  
Bga Packages ◽  
Silicon Thickness ◽  
Board Level

Abstract The standard requirement for FA Engineers needing to remove components from a board, prior to decapsulation or sample preparation, is shown to be greatly reduced, by the methods discussed here. By using a mechanical selected area preparation system with an open-design it is possible to reach all required areas of a large printed circuit board (PCB) or module to prepare a single component ‘in situ’. This makes subsequent optical or electrical testing faster and often more convenient to accomplish. Electronic End-pointing and 3D curvature compensation methods can often be used in parallel with sample prep techniques to further improve the consistency and efficacy of the decapsulation and thinning uniformity and final remaining silicon thickness (RST). Board level prep eliminates the worry of rework removal of BGA packages and the subsequent risk of damage to the device. Since the entire board is mounted, the contamination is restricted to the die surface and can be kept from the underside ball connections unlike current liquid immersion methods of package thinning or delayering. Since the camera is in line with the abrasion interface, imaging is real time during the entire milling and thinning process. Recent advances in automated tilt-table design have meant that a specific component’s angular orientation can be optimized for sample preparation. Improved tilt table technology also allows for improved mounting capability for boards of many types and sizes. The paper describes methods for decapsulation, thinning and backside polishing of a part ‘in situ’ on the polishing machine and allows the system to operate as a probe station for monitoring electrical characteristics while thinning. Considerations for designing board-level workholders are described – for boards that that are populated with components on one or even both sides. Using the techniques described, the quality of sample preparation and control is on a par with the processing of single package-level devices.

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