Board Level Drop Test Analysis Based on Modal Test and Simulation

2008 ◽  
Vol 130 (2) ◽  
Author(s):  
Fang Liu ◽  
Guang Meng ◽  
Mei Zhao ◽  
Junfeng Zhao
Keyword(s):  
Elastic Modulus ◽  
Dynamic Simulation ◽  
Printed Circuit Board ◽  
Digital Camera ◽  
Simulation Method ◽  
Drop Test ◽  
Circuit Board ◽  
Test Analysis ◽  
Test Board ◽  
Board Level

Solder joint reliability in drop test is crucial for handheld systems, such as mobile phone, digital camera, and MP3 player. In recent years, a lot of experiments and simulations have been carried out by researchers to study board level drop test, and many useful results have been obtained. Regarding mechanical simulation and analysis, there are still two challenges: How to design drop test printed circuit board (PCB) based on dynamic simulation and analysis? How to get accurate elastic modulus of PCB, especially damping parameters, as property inputs for drop test simulation? In this study, an approach based on systematic modal tests and analyses is used to address these two challenges. First, modal dynamic simulation is used to design the test board to meet drop test requirements. Second, modal tests are conducted on drop test board in order to validate dynamic simulation and measure structural damping parameters and overall board elastic modulus as well. Adopted directly in drop test simulation, the measured damping parameters and elastic modulus are proved to be accurate. It is verified through comparison between the finite element simulation and real drop test results. With the modal tests and simulation method established here, drop simulation becomes very simple and accurate, and test board design and characterization are also simplified. Thus, considerable drop test experiment and simulation fine tune, and validation work can be saved.

Numerical Model to Simulate the Drop Test of Printed Circuit Board (PCB)

2011 ◽  
Vol 423 ◽  
pp. 26-30
Author(s):  
S. Assif ◽  
M. Agouzoul ◽  
A. El Hami ◽  
O. Bendaou ◽  
Y. Gbati
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Drop Test ◽  
Dynamic Responses ◽  
Circuit Board ◽  
Joint Stress ◽  
Printed Circuit ◽  
Increasing Demand ◽  
Improved Model ◽  
Board Level

Increasing demand for smaller consumer electronic devices with multi-function capabilities has driven the packaging architectures trends for the finer-pitch interconnects, thus increasing chances of their failures. A simulation of the Board Level Drop-Test according to JEDEC (Joint Electron Device Council) is performed to evaluate the solder joint reliability under drop impact test. After good insights to the physics of the problem, the results of the numerical analysis on a simple Euler-Bernoulli beam were validated against analytical analysis. Since the simulation has to be performed on ANSYS Mechanical which is an implicit software, two methods were proposed, the acceleration-input and the displacement-input. The results are the same for both methods. Therefore, the simulation is carried on the real standard model construction of the board package level2. Then a new improved model is proposed to satisfy shape regular element and accuracy. All the models are validated to show excellent first level correlation on the dynamic responses of Printed Circuit Board, and second level correlation on solder joint stress. Then a static model useful for quick design analysis and optimization’s works is proposed and validated. Finally, plasticity behavior is introduced on the solder ball and a non-linear analysis is performed.

Failure Analysis of Halogen-Free Printed Circuit Board Assembly Under Board-Level Drop Test

2012 ◽  
Vol 134 (1) ◽  
Author(s):  
Hung-Jen Chang ◽  
Chau-Jie Zhan ◽  
Tao-Chih Chang ◽  
Jung-Hua Chou
Keyword(s):  
Printed Circuit Board ◽  
Drop Test ◽  
Circuit Board ◽  
Printed Circuit Board Assembly ◽  
Printed Circuit ◽  
Plastic Ball ◽  
Circuit Board Assembly ◽  
Halogen Free ◽  
Board Level ◽  
The Impact

In this study, a lead-free dummy plastic ball grid array component with daisy-chains and Sn4.0Ag0.5Cu Pb-free solder balls was assembled on an halogen-free high density interconnection printed circuit board (PCB) by using Sn1.0Ag0.5Cu solder paste on the Cu pad surfaces of either organic solderable preservative (OSP) or electroless nickel immersion gold (ENIG). The assembly was tested for the effect of the formation extent of Ag3Sn intermetallic compound. Afterward a board-level pulse-controlled drop test was conducted on the as-reflowed assemblies according to the JESD22-B110 and JESD22-B111 standards, the impact performance of various surface finished halogen-free printed circuit board assembly was evaluated. The test results showed that most of the fractures occurred around the pad on the test board first. Then cracks propagated across the outer build-up layer. Finally, the inner copper trace was fractured due to the propagated cracks, resulting in the failure of the PCB side. Interfacial stresses numerically obtained by the transient stress responses supported the test observation as the simulated initial crack position was the same as that observed.

Assessment of Fatigue Induced Pad Cratering With a Universal Expression of Printed Circuit Board Fatigue Resistance

2020 ◽  
Vol 142 (2) ◽  
Author(s):  
Qiming Zhang ◽  
S. W. Ricky Lee
Keyword(s):  
Printed Circuit Board ◽  
Drop Test ◽  
Circuit Board ◽  
Bending Test ◽  
Cyclic Bending ◽  
Pcb Assembly ◽  
Testing Method ◽  
Pad Cratering ◽  
Drop Tests ◽  
Board Level

Abstract Repeated loading is an important reason to cause pad cratering fatigue failure in ball grid array (BGA) device in printed circuit board (PCB) assembly. For industry application, the board level drop test is commonly applied to evaluate the pad cratering fatigue strength under the repetitive drop loading. Although this testing method is consistent with the actual service condition of BGA-PCB assembly, it is extremely time consuming in the testing operation and expensive in costs. Another fatigue evaluation testing method for BGA-PCB assembly is the board level cyclic bending test. Compare with the board level drop test, this testing method can be handled by universal testing machine automatically without manual operation during the testing process. In consequence, the cyclic bending test has the merits of simple, fast, and low costs, and it is always desirable to evaluate the repeated drop life of pad cratering with cyclic bending test. This research proposes a correlation between the cyclic bending and repetitive drop test in BGA-PCB assemblies. With assistance of finite element method, the equivalent cyclic bending testing conditions of drop tests are developed. The experimental validation is also conducted to prove accuracy of the correlation. From the analysis of finite element method and experiments, both cyclic bending tests and repetitive drop tests agree with the same strain–number of cycle (S–N) curve. This means the S–N curve can be treated as a generalized failure criterion of fatigue induced pad cratering. The conclusion is crucial for reliability design phases to prevent the pad cratering fatigue failure.

In-Situ Mechanical Sample Preparation of Selected Sites and Components on Large Modules and Boards

2016 ◽  
Author(s):  
Jim Colvin ◽  
Timothy Hazeldine ◽  
Heenal Patel
Keyword(s):  
Sample Preparation ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Tilt Table ◽  
Standard Requirement ◽  
Open Design ◽  
Bga Packages ◽  
Silicon Thickness ◽  
Board Level

Abstract The standard requirement for FA Engineers needing to remove components from a board, prior to decapsulation or sample preparation, is shown to be greatly reduced, by the methods discussed here. By using a mechanical selected area preparation system with an open-design it is possible to reach all required areas of a large printed circuit board (PCB) or module to prepare a single component ‘in situ’. This makes subsequent optical or electrical testing faster and often more convenient to accomplish. Electronic End-pointing and 3D curvature compensation methods can often be used in parallel with sample prep techniques to further improve the consistency and efficacy of the decapsulation and thinning uniformity and final remaining silicon thickness (RST). Board level prep eliminates the worry of rework removal of BGA packages and the subsequent risk of damage to the device. Since the entire board is mounted, the contamination is restricted to the die surface and can be kept from the underside ball connections unlike current liquid immersion methods of package thinning or delayering. Since the camera is in line with the abrasion interface, imaging is real time during the entire milling and thinning process. Recent advances in automated tilt-table design have meant that a specific component’s angular orientation can be optimized for sample preparation. Improved tilt table technology also allows for improved mounting capability for boards of many types and sizes. The paper describes methods for decapsulation, thinning and backside polishing of a part ‘in situ’ on the polishing machine and allows the system to operate as a probe station for monitoring electrical characteristics while thinning. Considerations for designing board-level workholders are described – for boards that that are populated with components on one or even both sides. Using the techniques described, the quality of sample preparation and control is on a par with the processing of single package-level devices.

Experimental Investigation by Speckle Interferometry of Solder Joint Failure Under Thermomechanical Load Aggravated by Boundary Conditions at Board Level

2012 ◽  
Vol 134 (4) ◽  
Author(s):  
D. N. Borza ◽  
I. T. Nistea
Keyword(s):  
Solder Joint ◽  
Fundamental Frequency ◽  
Printed Circuit Board ◽  
Speckle Interferometry ◽  
Circuit Board ◽  
Joint Failure ◽  
Printed Circuit ◽  
Out Of Plane ◽  
Fringe Patterns ◽  
Board Level

Reliability of electronic assemblies at board level and solder joint integrity depend upon the stress applied to the assembly. The stress is often of thermomechanical or of vibrational nature. In both cases, the behavior of the assembly is strongly influenced by the mechanical boundary conditions created by the printed circuit board (PCB) to casing fasteners. In many previously published papers, the conditions imposed to the fasteners are mostly aiming at an increase of the fundamental frequency and a decrease of static or dynamic displacement values characterizing the deformation. These conditions aim at reducing the fatigue in different parts of these assemblies. In the photomechanics laboratory of INSA Rouen, the origins of solder joint failure have been investigated by means of full-field measurements of the flexure deformation induced by vibrations or by forced thermal convection. The measurements were done both at a global level for the whole printed circuit board assembly (PCBA) and at a local level at the solder joints where failure was reported. The experimental technique used was phase-stepped laser speckle interferometry. This technique has a submicrometer sensitivity with respect to out-of-plane deformations induced by bending and its use is completely nonintrusive. Some of the results were comforted by comparison with a numerical finite elements model. The experimental results are presented either as time-average holographic fringe patterns, as in the case of vibrations, or as wrapped phase patterns, as in the case of deformation under thermomechanical stress. Both types of fringe patterns may be processed so as to obtain the explicit out-of-plane static deformation (or vibration amplitude) maps. Experimental results show that the direct cause of solder joint failure may be a high local PCB curvature produced by a supplementary fastening screw intended to reduce displacements and increase fundamental frequency. The curvature is directly responsible for tensile stress appearing in the leads of a large quad flat pack (QFP) component and for shear in the corresponding solder joints. The general principle of increasing the fundamental frequency and decreasing the static or dynamic displacement values has to be checked against the consequences on the PCB curvature near large electronic devices having high stiffness.

Numerical Simulation and Experimental Measurement of a Printed Circuit Board Subjected to Drop Test

2009 ◽  
Vol 419-420 ◽  
pp. 37-40
Author(s):  
Shiuh Chuan Her ◽  
Shien Chin Lan ◽  
Chun Yen Liu ◽  
Bo Ren Yao
Keyword(s):  
Finite Element ◽  
Experimental Measurement ◽  
Test Specimen ◽  
Printed Circuit Board ◽  
Drop Impact ◽  
Simulation Technique ◽  
Drop Test ◽  
Circuit Board ◽  
Printed Circuit ◽  
The Impact

Drop test is one of the common methods for determining the reliability of electronic products under actual transportation conditions. The aim of this study is to develop a reliable drop impact simulation technique. The test specimen of a printed circuit board is clamped at two edges on a test fixture and mounted on the drop test machine platform. The drop table is raised at the height of 50mm and dropped with free fall to impinge four half-spheres of Teflon. One accelerometer is mounted on the center of the specimen to measure the impact pulse. The commercial finite element software ANSYS/LS-DYNA is applied to compute the impact acceleration and dynamic strain on the test specimen during the drop impact. The finite element results are compared to the experimental measurement of acceleration with good correlation between simulation and drop testing. With the accurate simulation technique, one is capable of predicting the impact response and characterizing the failure mode prior to real reliability test.

Review of Printed-Circuit-Board Level EMI/EMC Issues and Tools

2010 ◽  
Vol 52 (2) ◽  
pp. 455-461 ◽  
Author(s):  
Bruce Archambeault ◽  
Colin Brench ◽  
Sam Connor
Keyword(s):  
Printed Circuit Board ◽  
Circuit Board ◽  
Printed Circuit ◽  
Board Level

I/O Printed Circuit Board Assemblies; Recent Learning in Mechanical Stress Analysis, Verification Testing, and Post-test Analysis Techniques and Results

2015 ◽  
Vol 2015 (1) ◽  
pp. 000169-000178
Author(s):  
John Torok ◽  
Shawn Canfield ◽  
Suraush Khambati ◽  
Robert Mullady ◽  
Budy Notohardjono ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Measurement Techniques ◽  
Form Factors ◽  
Mechanical Analysis ◽  
Circuit Board ◽  
Mechanical Shock ◽  
Test Analysis ◽  
Printed Circuit ◽  
Analysis Techniques ◽  
Post Test

Recent high-end server designs have included new Input / Output (I/O) printed circuit board (PCB) assemblies consisting of a variety of form factors, electronic design layouts, and packaging assembly characteristics. To insure the required functional and reliability aspects are established and maintained, new mechanical analysis and verification testing techniques have been recently devised. A description of the design application set, the analysis tools and techniques applied, and the verification testing completed, including the associated measurement techniques as well as post-testing analysis methods and results are presented. Also included are the recent PCB raw card characterization efforts whose results have been applied as material property inputs to the analysis to improve analytical-to-empirical correlation. Included within the application set are both the use of custom designed cards as well as industry standard, original equipment manufacturer (OEM) cards that are packaged within custom enclosures. Given packaged and unpackaged (i.e., as installed in a higher-level rack system assembly) fragility testing requirements, new analysis techniques exploiting the capabilities of LS-DYNA have been used to provide a predictive means to support both initial as well as iterative design levels. In addition, these analysis results are also used to identify locations for measurement sensor placement employed during mechanical verification testing. Thermal shock and mechanical shock and vibration verification testing details and results are provided describing the conditions applied to simulate assembly shipping conditions, both as packaged as well as in situ to the higher-level of assembly. Included with this is a discussion with respect to post-test analysis techniques and results, including the use of both microscopic cross-section analysis as well as dye-pry assessments. Concluding, continued and future activities are described as “best practices” for the application of this methodology as part of the end-to-end development process.

High-Speed Cyclic Bend Tests and Board-Level Drop Tests for Evaluating the Robustness of Solder Joints in Printed Circuit Board Assemblies

2009 ◽  
Vol 38 (6) ◽  
pp. 884-895 ◽  
Author(s):  
E.H. Wong ◽  
S.K.W. Seah ◽  
C.S. Selvanayagam ◽  
R. Rajoo ◽  
W.D. van Driel ◽  
...  
Keyword(s):  
High Speed ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Printed Circuit ◽  
Drop Tests ◽  
Bend Tests ◽  
Board Level
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