Ultraminiaturized Three-Dimensional IPAC Packages With 100 μm Thick Glass Substrates for Radio Frequency Front-End Modules

2017 ◽  
Vol 139 (4) ◽  
Author(s):  
Zihan Wu ◽  
Junki Min ◽  
Vanessa Smet ◽  
Markondeya Raj Pulugurtha ◽  
Venky Sundaram ◽  
...  
Keyword(s):  
Radio Frequency ◽  
Printed Circuit Board ◽  
Impedance Matching ◽  
Three Dimensional ◽  
Circuit Board ◽  
Electrical Performance ◽  
Active Components ◽  
Glass Substrates ◽  
Matching Networks ◽  
Front End

This paper presents innovative compact three-dimensional integrated passive and active components (3D IPAC) packages with ultrathin glass substrates for radio frequency (RF) long-term evolution (LTE) front-end modules (FEMs). High component density was achieved through double-side integration of substrate-embedded passives for impedance matching networks and three-dimensional (3D) double-side assembly of filters onto glass substrates. Glass with 100 μm thickness formed the core of the package, while four build-up layers with 15 μm thickness each were used to embed passives and form redistribution layers (RDLs). Advanced panel-scale double-side assembly processes were developed with low-cost mass reflow. Board-level assembly was realized with paste-printed solder balls and reflow on printed circuit board (PCB) with no intermediate substrates. Electrical performance of filters with substrate-embedded impedance matching networks was characterized and compared to simulations.

Microhardness Testing on Via Fill Material for Via In Pad Technology

2003 ◽  
Author(s):  
Norman J. Armendariz ◽  
Carolyn McCormick
Keyword(s):  
Printed Circuit Board ◽  
Failure Modes ◽  
Strong Dependence ◽  
Circuit Board ◽  
Electrical Performance ◽  
Gravimetric Analysis ◽  
Passive Components ◽  
Root Cause ◽  
Fill Material ◽  
Signal Routing

Abstract Via in pad PCB (Printed Circuit board) technology for passive components such as chip capacitors and resistors, provides the potential for improved signal routing density and reduced PCB area. Because of these improvements there is the potential for PCB cost reduction as well as gains in electrical performance through reduced impedance and inductance. However, not long after the implementation, double digit unit failures for solder joint electrical opens due to capacitor “tombstoning” began to occur. Failure modes included via fill material (solder mask) protrusion from the via as well as “out gassing” and related “tombstoning.” This failure analysis involved investigating a strong dependence on PCB supplier and, less obviously, manufacturing site. Other factors evaluated included via fill material, drill size, via fill thermal history and via fill amount or fill percent. The factor most implicated was incomplete cure of the via fill material. Previous thermal gravimetric analysis methods to determine level of polymerization or cure did not provide an ability to measure and demonstrate via fill cure level in small selected areas or its link to the failures. As a result, there was a metrology approach developed to establish this link and root-cause the failures in the field, which was based on microhardness techniques and noncontact via fill measuring metrologies.

scholarly journals Optimum power transfer in RF front end systems using adaptive impedance matching technique

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Mohammad Alibakhshikenari ◽  
Bal S. Virdee ◽  
Leyre Azpilicueta ◽  
Chan H. See ◽  
Raed Abd-Alhameed ◽  
...  
Keyword(s):  
Impedance Matching ◽  
Adaptive Antenna ◽  
Power Transfer ◽  
Control Loops ◽  
Matching Networks ◽  
Front End ◽  
Rf Front End ◽  
Matching Technique ◽  
Digital Circuitry ◽  
Communications System

AbstractMatching the antenna’s impedance to the RF-front-end of a wireless communications system is challenging as the impedance varies with its surround environment. Autonomously matching the antenna to the RF-front-end is therefore essential to optimize power transfer and thereby maintain the antenna’s radiation efficiency. This paper presents a theoretical technique for automatically tuning an LC impedance matching network that compensates antenna mismatch presented to the RF-front-end. The proposed technique converges to a matching point without the need of complex mathematical modelling of the system comprising of non-linear control elements. Digital circuitry is used to implement the required matching circuit. Reliable convergence is achieved within the tuning range of the LC-network using control-loops that can independently control the LC impedance. An algorithm based on the proposed technique was used to verify its effectiveness with various antenna loads. Mismatch error of the technique is less than 0.2%. The technique enables speedy convergence (< 5 µs) and is highly accurate for autonomous adaptive antenna matching networks.

Three Dimensional Detection of the via in the PCB CT Image Using Morphology Operation

2015 ◽  
Vol 752-753 ◽  
pp. 1406-1412
Author(s):  
Lei Zeng ◽  
Jian Chen ◽  
Han Ning Li ◽  
Bin Yan ◽  
Yi Fu Xu ◽  
...  
Keyword(s):  
Nondestructive Testing ◽  
Printed Circuit Board ◽  
Three Dimensional ◽  
Detection Algorithm ◽  
Circuit Board ◽  
Dimensional Structure ◽  
Three Dimension ◽  
Shape Information ◽  
Printed Circuit ◽  
Testing Technology

In modern industry, the nondestructive testing of printed circuit board (PCB) can prevent effectively the system failure and is becoming more and more important. As a vital part of the PCB, the via connects the devices, the components and the wires and plays a very important role for the connection of the circuits. With the development of testing technology, the nondestructive testing of the via extends from two dimension to three dimension in recent years. This paper proposes a three dimensional detection algorithm using morphology method to test the via. The proposed algorithm takes full advantage of the three dimensional structure and shape information of the via. We have used the proposed method to detect via from PCB images with different size and quality, and found the detection performances to be very encouraging.

Numerical Investigation of Heat Transfer of Twelve Plastic Leaded Chip Carrier (PLCC) by Using Computational Fluid Dynamic, FLUENTTM Software

2013 ◽  
Vol 795 ◽  
pp. 603-610 ◽  
Author(s):  
Mohamed Mazlan ◽  
A. Rahim ◽  
M.A. Iqbal ◽  
Mohd Mustafa Al Bakri Abdullah ◽  
W. Razak ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Fluid Dynamic ◽  
Three Dimensional ◽  
Circuit Board ◽  
Junction Temperature ◽  
Inlet Velocity ◽  
Chip Carrier ◽  
Flow Through ◽  
Package Density ◽  
Heat And Fluid Flow

Plastic Leaded Chip Carrier (PLCC) package has been emerged a promising option to tackle the thermal management issue of micro-electronic devices. In the present study, three dimensional numerical analysis of heat and fluid flow through PLCC packages oriented in-line and mounted horizontally on a printed circuit board, is carried out using a commercial CFD code, FLUENTTM. The simulation is performed for 12 PLCC under different inlet velocities and chip powers. The contours of average junction temperatures are obtained for each package under different conditions. It is observed that the junction temperature of the packages decreases with increase in inlet velocity and increases with chip power. Moreover, the increase in package density significantly contributed to rise in temperature of chips. Thus the present simulation demonstrates that the chip density (the number of packages mounted on a given area), chip power and the coolant inlet velocity are strongly interconnected; hence their appropriate choice would be crucial.

Integration of a K-Band Receiver Front-End Using a Copper Core Printed Circuit Board

2018 ◽  
Vol 2018 (1) ◽  
pp. 000384-000388
Author(s):  
Brian Curran ◽  
Jacob Reyes ◽  
Christian Tschoban ◽  
Ivan Ndip ◽  
Klaus-Dieter Lang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Antenna Arrays ◽  
High Frequency ◽  
Printed Circuit Board ◽  
Cost Effective ◽  
Circuit Board ◽  
Front End ◽  
High Bandwidth ◽  
Increasing Demand ◽  
K Band

Abstract Increasing demand for high bandwidth wireless satellite connections and telecommunications has resulted in interest in steerable antenna arrays in the GHz frequency range. These applications require cost-effective integration technologies for high frequency and high power integrated circuits (ICs) using GaAs, for example. In this paper, an integration platform is proposed, that enables GaAs ICs to be directly placed on a copper core inside cavities of a high frequency laminate for optimal cooling purposes. The platform is used to integrate a K-Band receiver front-end, composed of four GaAs ICs, with linear IF output power for input powers above −40dBm and a temperature of 42°C during operation.

Comparison of Different Methods for Stress and Deflection Analysis in Embedded Die Packages during the Assembly Process

2014 ◽  
Vol 2014 (1) ◽  
pp. 000355-000360
Author(s):  
K. Macurova ◽  
R. Bermejo ◽  
M. Pletz ◽  
R. Schöngrundner ◽  
T. Antretter ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Plastic Material ◽  
Three Dimensional ◽  
Diffraction Method ◽  
Element Model ◽  
Analytical Investigation ◽  
Circuit Board ◽  
Curvature Radius ◽  
Assembly Process ◽  
Deflection Analysis

Important topics for electronic packages are thermally induced stresses created during package manufacturing and their role in mechanical failure. In the present paper, an analytical and a numerical analysis of the assembly process (component attached with an adhesive to a copper foil) is investigated. This process is prior to the lamination of the printed circuit board. Stresses develop due to a mismatch of coefficients of thermal expansion and particularly to shrinkage associated with adhesive polymerization. The analytical investigation is based on the classical laminate theory and an interfacial model. The three-dimensional numerical finite element model is capable to use geometric and material properties which are not possible to investigate analytically. In particular, the influence of the adhesive meniscus and plastic material models for copper and adhesive are investigated. The models are validated experimentally by an X-ray diffraction method (Rocking-Curve-Technique) showing a good agreement of the calculated and measured curvature radius values.

Comparison of Different Methods for Stress and Deflection Analysis in Embedded Die Packages During the Assembly Process

2015 ◽  
Vol 12 (2) ◽  
pp. 80-85 ◽  
Author(s):  
K. Macurova ◽  
R. Bermejo ◽  
M. Pletz ◽  
R. Schöngrundner ◽  
T. Antretter ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Plastic Material ◽  
Three Dimensional ◽  
Diffraction Method ◽  
Element Model ◽  
Analytical Investigation ◽  
Circuit Board ◽  
Curvature Radius ◽  
Assembly Process ◽  
Deflection Analysis

Important topics for electronic packages are thermally induced stresses created during package manufacturing and their role in mechanical failure. In the present paper, an analytical and a numerical analysis of the assembly process (component attached with an adhesive to a copper foil) is investigated. This process is prior to the lamination of the printed circuit board. Stresses develop due to a mismatch of coefficients of thermal expansion and particularly to shrinkage associated with adhesive polymerization. The analytical investigation is based on the classical laminate theory and an interfacial model. The three-dimensional, numerical, finite element model is capable of using geometric and material properties not possible to investigate analytically. In particular, the influence of the adhesive meniscus and plastic material models for copper and adhesive are investigated. The models are validated experimentally by an x-ray diffraction method (rocking-curve technique) showing a good agreement of the calculated and measured curvature radius values.

High quality factor fractal inductor with complementary split-ring array inclusion

Circuit World ◽  
2020 ◽  
Vol 46 (3) ◽  
pp. 215-219
Author(s):  
Akhendra Kumar Padavala ◽  
Narayana Kiran Akondi ◽  
Bheema Rao Nistala
Keyword(s):  
Quality Factor ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Three Dimensional ◽  
Circuit Board ◽  
Integrated Circuit Design ◽  
Split Ring ◽  
Content Type ◽  
Practical Implications

Purpose This paper aims to present an efficient method to improve quality factor of printed fractal inductors based on electromagnetic band-gap (EBG) surface. Design/methodology/approach Hilbert fractal inductor is designed and simulated using high-frequency structural simulator. To improve the quality factor, an EBG surface underneath the inductor is incorporated without any degradation in inductance value. Findings The proposed inductor and Q factor are measured based on well-known three-dimensional simulator, and the results are compared experimentally. Practical implications The proposed method was able to significantly decrease the noise with increase in the speed of radio frequency and sensor-integrated circuit design. Originality/value Fractal inductor is designed and simulated with and without EBG surfaces. The measurement of printed circuit board prototypes demonstrates that the inclusion of split-ring array as EBG surface increases the quality factor by 90 per cent over standard fractal inductor of the same dimensions with a small degradation in inductance value and is capable of operating up to 2.4 GHz frequency range.

scholarly journals An Integrated Front-end Circuit Board for Air-Coupled CMUT Burst-Echo Imaging

Sensors ◽  
2020 ◽  
Vol 20 (21) ◽  
pp. 6128
Author(s):  
Lei Ye ◽  
Jian Li ◽  
Hui Zhang ◽  
Dongmei Liang ◽  
Zhuochen Wang
Keyword(s):  
Imaging System ◽  
Signal To Noise Ratio ◽  
Three Dimensional ◽  
Ultrasonic Transducers ◽  
Circuit Board ◽  
Capacitive Micromachined Ultrasonic Transducers ◽  
Front End ◽  
Field Programmable ◽  
Good Potential ◽  
Dc Bias

To conduct burst-echo imaging with air-coupled capacitive micromachined ultrasonic transducers (CMUTs) using the same elements in transmission and reception, this work proposes a dedicated and integrated front-end circuit board design to build an imaging system. To the best of the authors’ knowledge, this is the first air-coupled CMUT burst-echo imaging using the same elements in transmission and reception. The reported front-end circuit board, controlled by field programmable gate array (FPGA), consisted of four parts: an on-board pulser, a bias-tee, a T/R switch and an amplifier. Working with our 217 kHz 16-element air-coupled CMUT array under 100 V DC bias, the front-end circuit board and imaging system could achieve 22.94 dB signal-to-noise ratio (SNR) in burst-echo imaging in air, which could represent the surface morphology and the three-dimensional form factor of the target. In addition, the burst-echo imaging range of our air-coupled CMUT imaging system, which could work between 52 and 273 mm, was discussed. This work suggests good potential for ultrasound imaging and gesture recognition applications.

Sign in / Sign up

Export Citation Format

Share Document