Embedded Two-Phase Cooling of Large Three-Dimensional Compatible Chips With Radial Channels

2016 ◽  
Vol 138 (2) ◽  
Author(s):  
Mark Schultz ◽  
Fanghao Yang ◽  
Evan Colgan ◽  
Robert Polastre ◽  
Bing Dang ◽  
...  

Thermal performance for embedded two-phase cooling using dielectric coolant (R1234ze) is evaluated on a ∼20 mm × 20 mm large die. The test vehicles incorporate radial expanding channels with embedded pin fields suitable for through-silicon-via (TSV) interconnects of multidie stacks. Power generating features mimicking those anticipated in future generations of processor chips with eight cores are included. Initial results show that for the types of power maps anticipated, critical heat fluxes (CHFs) in “core” areas of at least 350 W/cm2 with at least 20 W/cm2 “background” heating in rest of the chip area can be achieved with less than 30 °C temperature rise over the inlet coolant temperature. These heat fluxes are significantly higher than those seen for relatively long parallel channel devices of similar base channel dimensions. Experimental results of flow rate, pressure drop, “device,” and coolant temperature are also provided for these test vehicles along with details of the test facility developed to properly characterize the test vehicles.

Author(s):  
Mark Schultz ◽  
Fanghao Yang ◽  
Evan Colgan ◽  
Robert Polastre ◽  
Bing Dang ◽  
...  

Thermal performance for embedded two phase cooling using dielectric coolant (R1234ze) is evaluated on a ∼20 mm × 20 mm large die. The test vehicles incorporate radial expanding channels with embedded pin fields suitable for through-silicon-via (TSV) interconnects of multi-die stacks. Power generating features mimicking those anticipated in future generations of processor chips with 8 cores are included. Initial results show that for the types of power maps anticipated, critical heat fluxes in “core” areas of at least 350 W/cm2 with at least 20 W/cm2 “background” heating in rest of the chip area can be achieved with less than 30 °C temperature rise over the inlet coolant temperature. These heat fluxes are significantly higher than those seen for relatively long parallel channel devices of similar base channel dimensions. Experimental results of flow rate, pressure drop, “device,” and coolant temperature are also provided for these test vehicles along with details of the test facility developed to properly characterize the test vehicles.


2010 ◽  
Vol 132 (4) ◽  
Author(s):  
Yoon Jo Kim ◽  
Yogendra K. Joshi ◽  
Andrei G. Fedorov ◽  
Young-Joon Lee ◽  
Sung-Kyu Lim

It is now widely recognized that the three-dimensional (3D) system integration is a key enabling technology to achieve the performance needs of future microprocessor integrated circuits (ICs). To provide modular thermal management in 3D-stacked ICs, the interlayer microfluidic cooling scheme is adopted and analyzed in this study focusing on a single cooling layer performance. The effects of cooling mode (single-phase versus phase-change) and stack/layer geometry on thermal management performance are quantitatively analyzed, and implications on the through-silicon-via scaling and electrical interconnect congestion are discussed. Also, the thermal and hydraulic performance of several two-phase refrigerants is discussed in comparison with single-phase cooling. The results show that the large internal pressure and the pumping pressure drop are significant limiting factors, along with significant mass flow rate maldistribution due to the presence of hot-spots. Nevertheless, two-phase cooling using R123 and R245ca refrigerants yields superior performance to single-phase cooling for the hot-spot fluxes approaching ∼300 W/cm2. In general, a hybrid cooling scheme with a dedicated approach to the hot-spot thermal management should greatly improve the two-phase cooling system performance and reliability by enabling a cooling-load-matched thermal design and by suppressing the mass flow rate maldistribution within the cooling layer.


2015 ◽  
Vol 137 (4) ◽  
Author(s):  
Craig Green ◽  
Peter Kottke ◽  
Xuefei Han ◽  
Casey Woodrum ◽  
Thomas Sarvey ◽  
...  

Three-dimensional (3D) stacked electronics present significant advantages from an electrical design perspective, ranging from shorter interconnect lengths to enabling heterogeneous integration. However, multitier stacking exacerbates an already difficult thermal problem. Localized hotspots within individual tiers can provide an additional challenge when the high heat flux region is buried within the stack. Numerous investigations have been launched in the previous decade seeking to develop cooling solutions that can be integrated within the 3D stack, allowing the cooling to scale with the number of tiers in the system. Two-phase cooling is of particular interest, because the associated reduced flow rates may allow reduction in pumping power, and the saturated temperature condition of the coolant may offer enhanced device temperature uniformity. This paper presents a review of the advances in two-phase forced cooling in the past decade, with a focus on the challenges of integrating the technology in high heat flux 3D systems. A holistic approach is applied, considering not only the thermal performance of standalone cooling strategies but also coolant selection, fluidic routing, packaging, and system reliability. Finally, a cohesive approach to thermal design of an evaporative cooling based heat sink developed by the authors is presented, taking into account all of the integration considerations discussed previously. The thermal design seeks to achieve the dissipation of very large (in excess of 500 W/cm2) background heat fluxes over a large 1 cm × 1 cm chip area, as well as extreme (in excess of 2 kW/cm2) hotspot heat fluxes over small 200 μm × 200 μm areas, employing a hybrid design strategy that combines a micropin–fin heat sink for background cooling as well as localized, ultrathin microgaps for hotspot cooling.


Author(s):  
Daniel Lorenzini ◽  
Yogendra K. Joshi

Boiling systems are capable of dissipating high heat fluxes, and as such have potential applications in thermal management of high power microelectronics. Although there are a number of experimental investigations of flow boiling in small flow passages and several empirical correlations have been proposed, the computational fluid dynamics (CFD) modeling of such systems is much less explored. In the present investigation, a phase-change model representing the heat and mass transfer is coupled with the volume of fluid (VOF) model for the transient analysis of flow boiling. The analyzed domain consists of a silicon microchannel with a finite substrate thickness, subjected to non-uniform heat fluxes at localized regions, providing with a more realistic scenario for the case of microelectronics power maps. The results show the strong effect on the two-phase flow characteristics for these configurations and visualization of the induced flow regimes is presented. Furthermore, discussion about the heat transfer mechanisms, challenges and possible solutions are given in order to provide guidelines for effective cooling of these devices.


2014 ◽  
Vol 136 (2) ◽  
Author(s):  
Yassir Madhour ◽  
Brian P. d'Entremont ◽  
Jackson Braz Marcinichen ◽  
Bruno Michel ◽  
John Richard Thome

Three-dimensional (3D) stacking of integrated-circuit (IC) dies increases system density and package functionality by vertically integrating two or more dies with area-array through-silicon-vias (TSVs). This reduces the length of global interconnects and the signal delay time and allows improvements in energy efficiency. However, the accumulation of heat fluxes and thermal interface resistances is a major limitation of vertically integrated packages. Scalable cooling solutions, such as two-phase interlayer cooling, will be required to extend 3D stacks beyond the most modest numbers of dies. This paper introduces a realistic 3D chip stack along with a simulation method for the heat spreading and flow distribution among the channels of the evaporators. The model includes the significant sensitivity of each channel's friction factor to vapor quality, and hence mass flow to heat flux, which characterizes parallel two-phase flows. Simulation cases explore various placements of hot spots within the stack and effects which are unique to two-phase interlayer cooling. The results show that the effect of hot spots on individual dies can be mitigated by strong interlayer heat conduction if the relative position of the hot spots is selected carefully to result in a heat load and flow which are well balanced laterally.


Author(s):  
Sadegh Khalili ◽  
Srikanth Rangarajan ◽  
Bahgat Sammakia ◽  
Vadim Gektin

Abstract Increasing power densities in data centers due to the rise of Artificial Intelligence (AI), high-performance computing (HPC) and machine learning compel engineers to develop new cooling strategies and designs for high-density data centers. Two-phase cooling is one of the promising technologies which exploits the latent heat of the fluid. This technology is much more effective in removing high heat fluxes than when using the sensible heat of fluid and requires lower coolant flow rates. The latent heat also implies more uniformity in the temperature of a heated surface. Despite the benefits of two-phase cooling, the phase change adds complexities to a system when multiple evaporators (exposed to different heat fluxes potentially) are connected to one coolant distribution unit (CDU). In this paper, a commercial pumped two-phase cooling system is investigated in a rack level. Seventeen 2-rack unit (RU) servers from two distinct models are retrofitted and deployed in the rack. The flow rate and pressure distribution across the rack are studied in various filling ratios. Also, investigated is the transient behavior of the cooling system due to a step change in the information technology (IT) load.


Author(s):  
Pritish R. Parida

The information technology (IT) industry is exploring three-dimensional (3D) stacking of chips to maintain future computing scalability. However, 3D chip stacks require a solution to significant new thermal challenges. Interlayer two-phase evaporative cooling with a chip-to-chip interconnect-compatible dielectric fluid is an enabling technology but faces significant development issues. One such issue is the inability to thermally model a microprocessor with spatially varying heat sources together with a two phase microfluidic convection network. While progress has been made on two-phase conjugate simulations at the chip and channel levels, none of those provide a computationally manageable approach. In the present study, a reduced physics conjugate heat transfer model has been developed for simulating two-phase flow boiling through chip embedded micron scale cavities. This model has been validated with good accuracy against data available from literature. The validated model was then extended to predict the thermal performance of a state-of-the-art microprocessor chip with embedded two-phase cooling, where significant improvements in device junction temperatures were observed compared to the baseline cooling solution.


2018 ◽  
Vol 140 (3) ◽  
Author(s):  
Raphael K. Mandel ◽  
Daniel G. Bae ◽  
Michael M. Ohadi

The increasing heat densities in electronic components and focus on energy efficiency have motivated utilization of embedded two-phase cooling, which reduces system-level thermal resistance and pumping power. To achieve maximum benefit, high heat fluxes and vapor qualities should be achieved simultaneously. While many researchers have achieved heat fluxes in excess of 1 kW/cm2, vapor qualities are often below 10%, requiring a significantly large amount of energy spent on subcooling or pumping power, which minimizes the benefit of using two-phase thermal transport. In this work, we describe our recent work with cooling devices utilizing film evaporation with an enhanced fluid delivery system (FEEDS). The design, calibration, and experimental testing of a press-fit and bonded FEEDS test section are detailed here. Heat transfer and pressure drop performance was characterized and discussed. With the press-fit Si test chip, heat fluxes in excess of 1 kW/cm2 were obtained at vapor qualities approaching 45% and a coefficient of performance (COP) approaching 1400. With the bonded SiC test chip, heat fluxes in excess of 1 kW/cm2 were achieved at a vapor quality of 85% and heat densities approaching 490 W/cm3.


2020 ◽  
Vol 142 (4) ◽  
Author(s):  
Sadegh Khalili ◽  
Srikanth Rangarajan ◽  
Vadim Gektin ◽  
Husam Alissa ◽  
Bahgat Sammakia

Abstract Increasing power densities in data centers due to the rise of artificial intelligence, high-performance computing, and machine learning compel engineers to develop new cooling strategies and designs for high-performance information technology (IT) equipment. Two-phase cooling is a promising technology that exploits the latent heat of the coolant which is significantly more effective in removing high heat fluxes than when using the sensible heat of the fluid. Also, utilizing the latent heat allows operating at lower coolant flow rates and implies more uniformity in the temperature of heated surfaces. Despite the benefits of two-phase cooling, the phase change adds complexities to a system when multiple evaporators (exposed to different heat fluxes potentially) are connected to a single coolant distribution unit. In this article, a commercial coolant distribution unit is used to investigate pumped two-phase cooling in rack scale. Seventeen two-rack unit servers from two distinct models are retrofitted with 34 impinging jet evaporators and deployed in a rack. Four case studies are presented to provide insights into the complex behavior of a pumped two-phase cooling system with several evaporators. The flow rates and pressure distribution across the rack are studied in various filling ratios. Also, investigated is the transient behavior of the cooling system due to a step change in the IT workload. Finally, a control system is designed to regulate the temperature of the supplied coolant in response to the step change in the IT workload and is tested.


2017 ◽  
Vol 2017 ◽  
pp. 1-13
Author(s):  
Dong Hun Lee ◽  
Su Ryong Choi ◽  
Kwang Soon Ha ◽  
Han Young Yoon ◽  
Jae Jun Jeong

A core catcher has been developed to maintain the integrity of nuclear reactor containment from molten corium during a severe accident. It uses a two-phase natural circulation for cooling molten corium. Flow in a typical core catcher is unique because (i) it has an inclined cooling channel with downwards-facing heating surface, of which flow processes are not fully exploited, (ii) it is usually exposed to a low-pressure condition, where phase change causes dramatic changes in the flow, and (iii) the effects of a multidimensional flow are very large in the upper part of the core catcher. These features make computational analysis more difficult. In this study, the MARS code is assessed using the two-phase natural circulation experiments that had been conducted at the CE-PECS facility to verify the cooling performance of a core catcher. The code is a system-scale thermal-hydraulic (TH) code and has a multidimensional TH component. The facility was modeled by using both one- and three-dimensional components. Six experiments at the facility were selected to investigate the parametric effects of heat flux, pressure, and form loss. The results show that MARS can predict the two-phase flow at the facility reasonably well. However, some limitations are obviously revealed.


Sign in / Sign up

Export Citation Format

Share Document