A New Wafer Level Packaging Approach: Encapsulation, Metallization and Laser Structuring for Advanced System in Package Manufacturing

2005 ◽  
Vol 127 (1) ◽  
pp. 1-6 ◽  
Author(s):  
K.-F. Becker ◽  
T. Braun ◽  
A. Neumann ◽  
A. Ostmann ◽  
E. Coko ◽  
...  
Keyword(s):  
System Design ◽  
Process Development ◽  
Functional System ◽  
Single Chip ◽  
Wafer Level ◽  
Microelectronics Packaging ◽  
Flip Chips ◽  
Wafer Level Packaging ◽  
Electroless Process ◽  
Lead Free Solders

One of the general trends in microelectronics packaging is the constant miniaturization of devices. This has led to the development of maximum miniaturization of components on Si level, i.e., CSPs and Flip Chips. To further integrate more functionality into devices, and to further increase the degree of miniaturization, packaging development focus is switching from single chip packaging to the realization of systems in package, SiPs. Two main approaches do exist to realize this goal: one is to integrate all components into one dedicated package, yielding maximum miniaturization for a special application, but little flexibility as far as system design is concerned. The other is to create modular stackable components that can be assembled into a functional system. This integrates both flexibility in system design by exchangeable components and increased reliability potential, as single components can be tested separately. This last approach was considered a promising choice for the generation of SiPs. Within this paper a packaging process is introduced that allows the wafer level manufacturing of stackable, encapsulated devices. Using a transfer molded epoxy demonstrator, a proof-of-concept is performed showing the feasibility of the stackable package approach. This is achieved by combining wafer level encapsulation and molded interconnect device technology. An electroless process for metallization and laser techniques for structuring the metallization layer have been applied to generate structures for reliable interconnects capable for the use of lead-free solders. Summarized, this paper presents the process development and feasibility analysis of wafer level packaging technologies for modular SiP solutions based on a duromer MID approach.

Processing, Bumping and Assembly of Single Chip Plated Ni/Pd over ALCAP Bond Pads for Flip Chip Applications and Prototyping

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001841-001869
Author(s):  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
Paul N. Houston ◽  
Le hang La ◽  
Tim Spark
Keyword(s):  
Flip Chip ◽  
Process Development ◽  
Single Chip ◽  
Flip Chips ◽  
Chip Technology ◽  
Development Cycle ◽  
Before And After ◽  
Selective Plating ◽  
Bond Pads ◽  
Comprehensive Study

For Designer and Engineers, it is common during the process development cycle for new products to have limitations on the materials that are available for the prototype work. Most SMT devices are readily available in different formats/solder alloys to satisfy most of the needs for passive needs. However, many times IC devices are limited to what is available from the fab or an IC broker. These limitations can mean that die only come in aluminum, wirebond ready I/O metallization or that the silicon wafers already sawn and in single die formats. For applications where advancement in performance or miniaturization is needed, and the benefits of flip chip technology are attractive, then it is not trivial to be able to use these die. In these cases, the process of adding solderable plating technologies to the I/O bond pads is very favorable. The technologies are currently run for wafer lever plating baths, but very little has been done to evaluate single chip plating. Work in plating Ni/Pd onto the ALCAP structure has been performed to evaluate the process and feasibility of processing groups of singulated die with aluminum bond pads. The work to be detailed in this paper will go through the chemistries used in the plating process onto an aluminum bond pad that makes it suitable for flip chip processes. Several bumping structures, such as solder bumping over this plating technology and plating over gold or copper stud bumps, are evaluated. A process for bumping the flip chips is also detailed. The data for shear testing of the 10 variations before and after 500 liquid thermal shock cycles is detailed. Finally, a comprehensive study for assembly of solder bumped flip chips, with the selective plating process, will be detailed as well as a detailed analysis of the TC reliability of this assembly approach. It will be shown that selective Ni/Pd plating onto single, ALCAP bare die can allow for these typical wirebond die can be used in a practical approach solder flip chip process and provide reasonable reliability results when compared to a mainstream, wafer processed, solder bumped flip chip die.

Ultra Fine Pitch RDL Development in Multi-layer eWLB (embedded Wafer Level BGA) Packages

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 000809-000825
Author(s):  
Bernard Adams ◽  
Won Kyung Choi ◽  
Duk Ju Na ◽  
Andy Yong ◽  
Seung Wook Yoon ◽  
...  
Keyword(s):  
Line Width ◽  
High Performance ◽  
Process Development ◽  
Data Access ◽  
Electrical Performance ◽  
Logic Device ◽  
Wafer Level ◽  
Component Level ◽  
Wafer Level Packaging ◽  
Fine Pitch

The market for portable and mobile data access devices connected to a virtual cloud access point is exploding and driving increased functional convergence as well as increased packaging complexity and sophistication. This is creating unprecedented demand for higher input/output (I/O) density, higher bandwidths and low power consumption in smaller package sizes. There are exciting interconnect technologies in wafer level packaging such as eWLB (embedded Wafer Level Ball Grid Array), 2.5D interposers, thin PoP (Package-on-Package) and TSV (Through Silicon Via) interposer solutions to meet these needs. eWLB technologies with the ability to extend the package size beyond the area of the chip are leading the way to the next level of high density, thin packaging capability. eWLB provides a robust packaging platform supporting very dense interconnection and routing of multiple die in very reliable, low profile, low warpage 2.5D and 3D solutions. The use of these embedded eWLB packages in a side-by-side configuration to replace a stacked package configuration is critical to enable a more cost effective mobile market capability. Combining the analog or memory device with digital logic device in a semiconductor package can provide an optimum solution for achieving the best performance in thin, multiple-die integration aimed at very high performance. One of the greatest challenges facing wafer level packaging at present is the availability of routing and interconnecting high I/O fine pitch area array. RDL (redistribution layer) allows signal and supply I/O's to be redistributed to a footprint larger than the chip footprint in eWLB . Required line widths and spacing of 2/2 μm for eWLB applications support the bump pitch of less than 40um. Finer line width and spacing are critical for further design flexibility as well as electrical performance improvement. This paper highlights the rapidly moving trend towards eWLB packaging technologies with ultra fine 2/2um line width and line spacing and multi-layer RDL. A package design study, process development and optimization, and mechanical characterization will be discussed as well as test vehicle preparation. JEDEC component level reliability test results will also be presented.

Thin Glass Handling Solutions for Microelectronics Packaging

2020 ◽  
Vol 2020 (1) ◽  
pp. 000192-000196
Author(s):  
Aric Shorey ◽  
Shelby Nelson ◽  
David Levy ◽  
Paul Ballentine
Keyword(s):  
Wafer Level ◽  
Microelectronics Packaging ◽  
Thin Glass ◽  
Glass Substrates ◽  
Wafer Level Packaging ◽  
Fine Pitch ◽  
Temporary Bonding ◽  
Bonding Technology ◽  
Rf Loss ◽  
Grinding Operations

Abstract Glass substrates with fine-pitch through-glass via (TGV) technology gives an attractive approach to wafer level packaging and systems integration. Glass can be made in very thin sheets (<100 um thick) which aids in integration and eliminates the need for back-grinding operations. Electrical and physical properties of glass have many attractive attributes such as low RF loss, the ability to adjust thermal expansion properties, and low roughness with excellent flatness to achieve fine L/S. Furthermore, glass can be fabricated in panel format to reduce manufacturing costs. The biggest challenge to adopting glass as a packaging substrate has been the existence of gaps in the supply chain, caused primarily by the difficulty in handling large, thin glass substrates using standard automation and processing equipment. This paper presents a temporary bonding technology that allows the thin glass substrates to be processed in a semiconductor fab environment without the need to modify existing equipment.

Precise underfill dispense in high-throughput chip-on-wafer packaging

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-20
Author(s):  
Hanzhuang Liang
Keyword(s):  
Key Words ◽  
High Throughput ◽  
Cost Reduction ◽  
Flip Chip ◽  
Microelectronic Packaging ◽  
Portable Devices ◽  
Wafer Level ◽  
Flip Chips ◽  
Wafer Level Packaging ◽  
One Year

In today's microelectronic packaging, components are continuously designed smaller and assembled more densely to allow more functions to fit into compact portable devices. To enable this trend, more manufacturers are using flip chips that have more I/O's and smaller bumps sizes. This has introduced underfill dispensing that fills the gap between the flip chip and the substrate with polymer epoxy to help reduce thermal and mechanical stress at the bonding interface. In device packaging, the demands for cost reduction and miniaturization encourage the use of wafer-level packaging, such as the chip-on-wafer process. As a result, the challenges to this process have grown exponentially, and so have the challenges to underfill dispensing. For example, to package a device with a chip-last process, the keep-out-zone (KOZ) for underfill epoxy placement to nearby components is shrinking, e.g. from 700um to 300–500um within one year. A high-precision, high-throughput underfill dispensing process has been developed to conquer these challenges. This underfill process is being used in production for chip-on-wafer packaging. In one example, underfill must be dispensed within KOZ 300–500um at UPH 4000. New equipment and new dispensing techniques are under development to further push the limit on higher throughput and precision. Key words: underfill, dispense, microelectronic packaging, device packaging, wafer-level packaging, chip-on-wafer, chip-last, keep-out-zone, precision, throughput

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

3D IC/Stacked Device Fault Isolation Using 3D Magnetic Field Imaging

2014 ◽  
Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Fault Isolation ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Current Location ◽  
Geometrical Information ◽  
Magnetic Field Imaging ◽  
Silicon Vias ◽  
Non Destructive ◽  
Field Imaging

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

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