Evaluation of Thermal Enhancements to Flip-Chip-Plastic Ball Grid Array Packages

2004 ◽  
Vol 126 (4) ◽  
pp. 449-456 ◽  
Author(s):  
K. Ramakrishna ◽  
T.-Y. Tom Lee
Keyword(s):  
Thermal Conductivity ◽  
Thermal Resistance ◽  
Forced Convection ◽  
Thermal Performance ◽  
Flip Chip ◽  
Transfer Problem ◽  
Printed Wiring Board ◽  
Heat Spreader ◽  
Plastic Ball ◽  
Ball Grid Array Packages

Enhancements to thermal performance of FC-PBGA packages due to underfill thermal conductivity, controlled collapse chip connection (C4) pitch, package to printed wiring board (PWB) interconnection through thermal balls, a heat spreader on the backside of the die, and an overmolded die with and without a heat spreader have been studied by solving a conjugate heat transfer problem. These enhancements have been investigated under natural and forced convection conditions for freestream velocities up to 2 m/s. The following ranges of parameters have been covered in this study: substrate size: 25–35 mm, die size: 6.19×7.81 mm (48 mm2 area) and 9.13×12.95 mm (118 mm2 area), underfill thermal conductivity: 0.6–3.0 W/(m K), C4 pitch: 250 μm and below, no thermal balls to 9×9 array of thermal balls on 1.27 mm square pitch, and with copper heat spreader on the back of a bare and an overmolded die. Based on our previous work, predictions in this study are expected to be within ±10% of measured data. The conclusions of the study are: (i) Thermal conductivity of the underfill in the range 0.6 to 10 W/(m K) has negligible effect on thermal performance of FC-PBGA packages investigated here. (ii) Thermal resistances decrease 12–15% as C4 pitch decreases below 250 μm. This enhancement is smaller with increase in die area. (iii) Thermal balls connected to the PTHs in the PWB decrease thermal resistance of the package by 10–15% with 9×9 array of thermal balls and PTHs compared to no thermal balls. The effect of die size on this enhancement is more noticeable on junction to board thermal resistance, Ψjb, than the other two package thermal metrics. (iv) Heat spreader on the back of the die decreases junction-to-ambient thermal resistance, Θja, by 6% in natural convection and by 25% in forced convection. (v) An overmolded die with a heat spreader provides better a thermal enhancement than a heat spreader on a bare die for freestream velocities up to about 1 m/s. Beyond 1 m/s, a heat spreader on bare die has better thermal performance.

Thermal Assessment and Enhancement of Molded Array (MAP) PBGA Packages for Handheld Telecommunication Applications

2000 ◽  
Author(s):  
V. H. Adams ◽  
V. A. Chiriac ◽  
T.-Y. Tom Lee
Keyword(s):  
Thermal Conductivity ◽  
Thermal Resistance ◽  
Effective Thermal Conductivity ◽  
Thermal Performance ◽  
Transfer Problem ◽  
Effective Area ◽  
Printed Wiring Board ◽  
Heat Spreader ◽  
Fine Pitch ◽  
Plastic Ball

Abstract Computational Fluid Dynamics (CFD) simulations were conducted to characterize the thermal performance of Molded Array Plastic Ball Grid Array (MAP PBGA) packages for hand-held applications. Due to size constraints, these PBGA packages tend to have fine pitch solder ball arrays and small overall size. Thermal analysis is required to assess the design risks associated with this trend toward smaller size and increasing power dissipation requirements. A conjugate heat transfer problem, in which radiative losses from the exposed surfaces of the package and the printed wiring board to the walls of the wind tunnel, was solved for horizontal natural convection cooling conditions. Thermal model assumptions and development for the MAP PBGA package are provided. The model is benchmarked with measurements obtained for a 64 I/O 0.8 mm pitch, 8 mm MAP PBGA. Predictions for junction-to-ambient thermal resistance were within 10% of measured values. Baseline simulations were conducted for 0.8 mm pitch MAP PBGA packages with substrate/die size combinations in the range of 6 to 12 mm substrate size and 3.81 to 7.62 mm die size. Junction-to-ambient thermal resistances varied over the range of 28.8 °C/W to 62.4 °C/W. Methods to improve thermal performance of these packages were investigated. Previous work indicated that effective conduction to the substrate by heat spreaders, metallic lids, mold compound, heat sinks, and their combinations promoted thermal performance. A necessary further step is to understand how effective area for heat spreading inside the package affects its thermal behavior, while varying the die size for package configurations with and without heat spreader. Studies were conducted to evaluate thermal performance improvement through the use of a copper heat spreader on the package top surface as it is affected by die size, package size, and substrate effective thermal conductivity. Substrate effective thermal conductivity is varied through the use of two and four layer substrates with thermal vias under the die. Results show a modest 1% to 15% reduction in junction-to-ambient thermal resistance for the MAP PBGA package sizes of interest.

An Evaluation of Thermal Enhancements to Flip-Chip-Plastic Ball Grid Array (FC-PBGA) Packages

2003 ◽  
Author(s):  
K. Ramakrishna ◽  
T.-Y. Tom Lee
Keyword(s):  
Thermal Conductivity ◽  
Thermal Resistance ◽  
Thermal Performance ◽  
Flip Chip ◽  
Ball Grid Array ◽  
Heat Spreader ◽  
Thermal Enhancement ◽  
Plastic Ball ◽  
Plastic Ball Grid Array ◽  
Underfill Material

Flip-chip plastic ball grid array (FC-PBGA) packages are fast becoming the industry norm, in particular in the performance and cost driven consumer electronics sector. Since high thermal conductivity (k∼15–20 W/(m K)) ceramic substrate is replaced by a low conductivity (k∼0.2–0.5 W/(m K)) organic substrate in the FC-PBGA packages, enhancement of thermal performance of these packages to meet ever increasing demands is crucial for their wide spread use. In this study, enhancements to thermal performance of FC-PBGA packages due to material and design changes and external means such as heat spreaders and overmolding of the packages have been evaluated by solving a conjugate heat transfer models using the methods of computational fluid dynamic. The thermal enhancements evaluated in this study include the effect of thermal conductivity of the chip to package interconnect due to change in underfill material and the C4 bump pitch, effect of package to printed wiring board (PWB) interconnection through the use of thermal balls, effect of a heat spreader on the backside of the die, and overmolding the die without and with a heat spreader. Thermal performance of the FC-PBGA packages have been studied using junction to ambient thermal resistance, Θja, junction-to-board thermal resistance Ψjb, and junction to case thermal resistance ΨjT under natural and forced convection for freestream velocities up to 2 m/s and the for following ranges of parameters: Substrate size: 25 to 35 mm, die size: 6.19×7.81 mm (48 mm2 area) and 9.13×12.95 mm (118 mm2 area), C4 pitch: 250 mm, 150 mm and below, underfill material thermal conductivity: 0.6 to 3.0 W/(m K), no thermal balls between the package and the PWB to 9×9 array of thermal balls on 1.27 mm square pitch, and with copper heat spreader on the back of the bare and overmolded die. Based on previous experience, predictions in this study are expected to be within ±10% of measured data. The following conclusions are drawn from this study: 1. It is concluded that the thermal conductivity of the underfill materials in the range 0.6 to 10 W/(m K) is negligible. 2. It is also concluded that the bump pitch can decrease thermal resistances by 12 to 15 %. The change may be smaller with large die area. 3. Thermal balls (C5) connected to the PTHs in the PWB can decrease thermal resistance by about 10% to 15% as the number of thermal balls & PTHs increase zero to 9×9 on 1.27 mm pitch. The effect die size on this thermal enhancement is more noticeable on Ψjb. 4. Heat spreader on the back of the die decreases Θja by a small amount (6–7%) in natural convection and a large amount, about 25% in forced convection. 5. Overmolded die with heat spreader on the top of the overmold provides better thermal enhancement than heat spreader alone up to about 1 m/s. Beyond 1 m/s, heat spreader (without overmold) performs slightly better.

Prediction of Thermal Performance of Flip-Chip-Plastic Ball Grid Array (FC-PBGA) Packages: Effect of Die Size

2001 ◽  
Author(s):  
K. Ramakrishna ◽  
T.-Y. Lee
Keyword(s):  
Forced Convection ◽  
Thermal Performance ◽  
Flip Chip ◽  
Ball Grid Array ◽  
Thermal Parameters ◽  
Freestream Velocity ◽  
Asymptotic Values ◽  
Wide Range ◽  
Plastic Ball ◽  
Plastic Ball Grid Array

Abstract Package level thermal performance of flip-chip plastic ball grid array (FC-PBGA) packages has been predicted using experimentally validated mechanistic methodologies. The resulting conjugate heat transfer models have been solved using methods of computational fluid dynamics under natural and forced convection for freestream velocities up to 2 m/s. Overall junction to ambient, Θja, junction-to-board, Ψjb, and junction to case Ψjτ thermal resistances (here after referred to as thermal parameters) have been derived from the results of these computations. Using these models and methodologies, which are previously validated against experimental data, a parametric study of effect of die size on the package thermal parameters has been carried out for die sizes in the range 2 to 20 mm (area of 4–400 mm2) under natural and forced convection with freestream velocities in the range of 0.5 to 2 m/s. The predictions in this study are expected to be ±10% of the measured data. Based on this work the following conclusions have been drawn: 1. The junction to ambient, Θja, and junction to board, Ψjb, thermal resistances decrease with increase in freestream velocity, U, and junction to case thermal resistance, Ψjτ, increases with U. Ψjb shows a weaker dependence on U than Θja does. 2. For a fixed substrate size, package thermal resistances, Θja and Ψjb, decrease as the die size increases from 2 mm (4 mm2) to 20 mm (400 mm2). However, these resistances reach asymptotic values for die sizes above 50 mm2. The change in these resistances is in the range 20% to 35% and the effect of freestream velocity on the percentage changes is small. 3. An extensive database of experimentally validated FC-PBGA package thermal parameters have been generated for a wide range of die sizes.

Characterizing Bulk Thermal Conductivity and Interface Contact Resistance Effects of Thermal Interface Materials in Electronic Cooling Applications

2003 ◽  
Author(s):  
Vadim Gektin ◽  
Sai Ankireddi ◽  
Jim Jones ◽  
Stan Pecavar ◽  
Paul Hundt
Keyword(s):  
Thermal Conductivity ◽  
Thermal Resistance ◽  
Contact Resistance ◽  
Thermal Performance ◽  
Electronic Cooling ◽  
Thermal Interface Materials ◽  
Thermal Interface ◽  
Interface Contact ◽  
Interface Materials ◽  
Bulk Thermal Conductivity

Thermal Interface Materials (TIMs) are used as thermally conducting media to carry away the heat dissipated by an energy source (e.g. active circuitry on a silicon die). Thermal properties of these interface materials, specified on vendor datasheets, are obtained under conditions that rarely, if at all, represent real life environment. As such, they do not accurately portray the material thermal performance during a field operation. Furthermore, a thermal engineer has no a priori knowledge of how large, in addition to the bulk thermal resistance, the interface contact resistances are, and, hence, how much each influences the cooling strategy. In view of these issues, there exists a need for these materials/interfaces to be characterized experimentally through a series of controlled tests before starting on a thermal design. In this study we present one such characterization for a candidate thermal interface material used in an electronic cooling application. In a controlled test environment, package junction-to-case, Rjc, resistance measurements were obtained for various bondline thicknesses (BLTs) of an interface material over a range of die sizes. These measurements were then curve-fitted to obtain numerical models for the measured thermal resistance for a given die size. Based on the BLT and the associated thermal resistance, the bulk thermal conductivity of the TIM and the interface contact resistance were determined, using the approach described in the paper. The results of this study permit sensitivity analyses of BLT and its effect on thermal performance for future applications, and provide the ability to extrapolate the results obtained for the given die size to a different die size. The suggested methodology presents a readily adaptable approach for the characterization of TIMs and interface/contact resistances in the industry.

Integration of Silver Heat Spreaders in LTCC utilizing Thick Silver Tape in the Co-fire Process

2015 ◽  
Vol 2015 (CICMT) ◽  
pp. 000062-000066 ◽  
Author(s):  
T. Welker ◽  
S. Günschmann ◽  
N. Gutzeit ◽  
J. Müller
Keyword(s):  
Thermal Conductivity ◽  
Thermal Resistance ◽  
Heat Sink ◽  
Junction Temperature ◽  
Large Area ◽  
Heat Spreader ◽  
Integration Density ◽  
Heat Spreaders ◽  
Cte Mismatch ◽  
Pattern Resolution

The integration density in semiconductor devices is significantly increased in the last years. This trend is already described by Moore's law what forecasts a doubling of the integration density every two years. This evolution makes greater demands on the substrate technology which is used for the first level interconnect between the semiconductor and the device package. Higher pattern resolution is required to connect more functions on a smaller chip. Also the thermal performance of the substrate is a crucial issue. The increased integration density leads to an increased power density, what means that more heat has to dissipate on a smaller area. Thus, substrates with a high thermal conductivity (e. g. direct bonded copper (DBC)) are utilized which spread the heat over a large area. However, the reduced pattern resolution caused by thick metal layers is disadvantageous for this substrate technology. Alternatively, low temperature co-fired ceramic (LTCC) can be used. This multilayer technology provides a high pattern resolution in combination with a high integration grade. The poor thermal conductivity of LTCC (3 … 5 W*m−1*K−1) requires thermal vias made of silver paste which are placed between the power chip and the heat sink and reduce the thermal resistance of the substrate. The via-pitch and diameter is limited by the LTCC technology, what allows a maximum filling grade of approx. 20 to 25 %. Alternatively, an opening in the ceramic is created, to bond the chip directly to the heat sink. This leads to technological challenges like the CTE mismatch between the chip and the heat sink material. Expensive materials like copper molybdenum composites with matched CTE have to be used. In the presented investigation, a thick silver tape is used to form a thick silver heat spreader through the LTCC substrate. An opening is structured by laser cutting in the LTCC tape and filled with a laser cut silver tape. After lamination, the substrate is fired using a constraint sintering process. The bond strength of the silver to LTCC interface is approx. 5.6 MPa. The thermal resistance of the silver structure is measured by a thermal test chip (Delphi PST1, 2.5 mm × 2.5 mm) glued with a high thermal conducting epoxy to the silver structure. The chip contains a resistor and diodes to generate heat and to determine the junction temperature respectively. The backside of the test structure is temperature stabilized by a temperature controlled heat sink. The resulting thermal resistance is in the range of 1.1 K/W to 1.5 K/W depending on the length of silver structure (5 mm to 7 mm). Advantages of the presented heat spreader are the low thermal resistance and the good embedding capability in the co-fire LTCC process.

Thermo-Optic Tuning Efficiency of Micro Ring Resonators on Low Thermal Resistance Silicon Photonics Substrates

2017 ◽  
Author(s):  
Shenghui Lei ◽  
Alexandre Shen ◽  
Ryan Enright
Keyword(s):  
Thermal Conductivity ◽  
Thermal Resistance ◽  
Thermal Performance ◽  
Silicon Photonics ◽  
Communication Systems ◽  
Device Fabrication ◽  
Ring Resonators ◽  
Wide Range ◽  
Soi Substrates ◽  
The Impact

Silicon photonics has emerged as a scalable technology platform for future optotelectronic communication systems. However, the current use of SiO2-based silicon-on-insulator (SOI) substrates presents a thermal challenge to integrated active photonic components such as lasers and semiconductor optical amplifiers due to the poor thermal properties of the buried SiO2 optical cladding layer beneath these devices. To improve the thermal performance of these devices, it has been suggested that SiO2 be replaced with aluminum nitride (AlN); a dielectric with suitable optical properties to function as an effective optical cladding that, in its crystalline state, demonstrates a high thermal conductivity (∼100× larger than SiO2 in current SOI substrates). On the other hand, the tuning efficiencies of thermally-controlled optical resonators and phase adjusters, crucial components for widely tunable lasers and modulators, are directly proportional to the thermal resistance of these devices. Therefore, the low thermal conductivity buried SiO2 layer in the SOI substrate is beneficial. Moreover, to further improve the thermal performance of these devices air trenches have been used to further thermally isolate these devices, resulting in up to ∼10× increase in tuning efficiency. Here, we model the impact of changing the buried insulator on a SOI substrate from SiO2 to high quality AlN on the thermal performance of a MRR. We map out the thermal performance of the MRR over a wide range of under-etch levels using a thermo-electrical model that incorporates a pseudo-etching approach. The pseudo-etching model is based on the diffusion equation and distinguishes the regions where substrate material is removed during device fabrication. The simulations reveal the extent to which air trenches defined by a simple etch pattern around the MRR device can increase the thermal resistance of the device. We find a critical under-etch below which no benefit is found in terms of the MRR tuning efficiency. Above this critical under-etch, the tuning efficiency increases exponentially. For the SiO2-based MRR, the thermal resistance increases by ∼7.7× between the un-etched state up to the most extreme etch state. In the unetched state, the thermal resistance of the AlN-based MRR is only ∼4% of the SiO2-based MRR. At the extreme level of under-etch, the thermal resistance of the AlN-based MRR is still only ∼60% of the un-etched SiO2-based MRR. Our results suggest the need for a more complex MRR thermal isolation strategy to significantly improve tuning efficiencies if an AlN-based SOI substrate is used.

Multi-scale thermal modeling of glass interposer for mobile electronics application

2016 ◽  
Vol 26 (3/4) ◽  
pp. 1157-1171 ◽  
Author(s):  
Sangbeom Cho ◽  
Venky Sundaram ◽  
Rao Tummala ◽  
Yogendra Joshi
Keyword(s):  
Thermal Conductivity ◽  
Thermal Resistance ◽  
Effective Thermal Conductivity ◽  
Thermal Performance ◽  
Memory Bandwidth ◽  
Vapor Chamber ◽  
Packaging Technology ◽  
Content Type ◽  
Low Thermal Conductivity ◽  
Multi Scale

Purpose – The functionality of personal mobile electronics continues to increase, in turn driving the demand for higher logic-to-memory bandwidth. However, the number of inputs/outputs supported by the current packaging technology is limited by the smallest achievable electrical line spacing, and the associated noise performance. Also, a growing trend in mobile systems is for the memory chips to be stacked to address the growing demand for memory bandwidth, which in turn gives rise to heat removal challenges. The glass interposer substrate is a promising packaging technology to address these emerging demands, because of its many advantages over the traditional organic substrate technology. However, glass has a fundamental limitation, namely low thermal conductivity (∼1 W/m K). The purpose of this paper is to quantify the thermal performance of glass interposer-based electronic packages by solving a multi-scale heat transfer problem for an interposer structure. Also, this paper studies the possible improvement in thermal performance by integrating a fluidic heat spreader or vapor chamber within the interposer. Design/methodology/approach – This paper illustrates the multi-scale modeling approach applied for different components of the interposer, including Through Package Vias (TPVs) and copper traces. For geometrically intricate and repeating structures, such as interconnects and TPVs, the unit cell effective thermal conductivity approach was used. For non-repeating patterns, such as copper traces in redistribution layer, CAD drawing-based thermal resistance network analysis was used. At the end, the thermal performance of vapor chamber integrated within a glass interposer was estimated by using an enhanced effective thermal conductivity, calculated from the published thermal resistance data, in conjunction with the analytical expression for thermal resistance for a given geometry of the vapor chamber. Findings – The limitations arising from the low thermal conductivity of glass can be addressed by using copper structures and vapor chamber technology. Originality/value – A few reports can be found on thermal performance of glass interposers. However thermal characteristics of glass interposer with advanced cooling technology have not been reported.

Investigation on the Use of Nanofluids to Enhance Heat Pipe Performance

Solar Energy ◽  
2005 ◽  
Author(s):  
Tomer Israeli ◽  
T. Agami Reddy ◽  
Young I. Cho
Keyword(s):  
Thermal Conductivity ◽  
Surface Tension ◽  
Thermal Resistance ◽  
Copper Oxide ◽  
Heat Pipe ◽  
Thermal Performance ◽  
Experimental Studies ◽  
Heat Pipes ◽  
Thermal Network ◽  
Overall Resistance

This paper reports on preliminary experimental results on using nanofluids to enhance the thermal performance of heat pipes. Our experience with preparing copper oxide (CuO) nanofluids is described. Contrary to earlier studies which report infinite shelf life, we found that nanofluid stability lasted for about three weeks only; an issue which merits further study. We have also conducted various experiments to measure the variation of thermal conductivity and surface tension with CuO nanofluid concentration. Actual experiments on nanofluid heat pipes were also performed which indicated an average 12.5% decrease in the overall thermal resistance of the heat pipe using nanofluid of 3% vol concentration. This observed improvement is fairly consistent with our predictions using a simple analytical thermal network model for heat pipe overall resistance and the measured nanofluid conductivity. The results, though encouraging, need more careful and elaborate experimental studies before the evidence can be deemed conclusive.

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