Thermo-Optic Tuning Efficiency of Micro Ring Resonators on Low Thermal Resistance Silicon Photonics Substrates

Silicon photonics has emerged as a scalable technology platform for future optotelectronic communication systems. However, the current use of SiO2-based silicon-on-insulator (SOI) substrates presents a thermal challenge to integrated active photonic components such as lasers and semiconductor optical amplifiers due to the poor thermal properties of the buried SiO2 optical cladding layer beneath these devices. To improve the thermal performance of these devices, it has been suggested that SiO2 be replaced with aluminum nitride (AlN); a dielectric with suitable optical properties to function as an effective optical cladding that, in its crystalline state, demonstrates a high thermal conductivity (∼100× larger than SiO2 in current SOI substrates). On the other hand, the tuning efficiencies of thermally-controlled optical resonators and phase adjusters, crucial components for widely tunable lasers and modulators, are directly proportional to the thermal resistance of these devices. Therefore, the low thermal conductivity buried SiO2 layer in the SOI substrate is beneficial. Moreover, to further improve the thermal performance of these devices air trenches have been used to further thermally isolate these devices, resulting in up to ∼10× increase in tuning efficiency. Here, we model the impact of changing the buried insulator on a SOI substrate from SiO2 to high quality AlN on the thermal performance of a MRR. We map out the thermal performance of the MRR over a wide range of under-etch levels using a thermo-electrical model that incorporates a pseudo-etching approach. The pseudo-etching model is based on the diffusion equation and distinguishes the regions where substrate material is removed during device fabrication. The simulations reveal the extent to which air trenches defined by a simple etch pattern around the MRR device can increase the thermal resistance of the device. We find a critical under-etch below which no benefit is found in terms of the MRR tuning efficiency. Above this critical under-etch, the tuning efficiency increases exponentially. For the SiO2-based MRR, the thermal resistance increases by ∼7.7× between the un-etched state up to the most extreme etch state. In the unetched state, the thermal resistance of the AlN-based MRR is only ∼4% of the SiO2-based MRR. At the extreme level of under-etch, the thermal resistance of the AlN-based MRR is still only ∼60% of the un-etched SiO2-based MRR. Our results suggest the need for a more complex MRR thermal isolation strategy to significantly improve tuning efficiencies if an AlN-based SOI substrate is used.