Investigation of Variable Frequency Microwave Processing for Electronic Packaging Applications

2003 ◽  
Vol 125 (2) ◽  
pp. 294-301 ◽  
Author(s):  
Patricia F. Mead ◽  
Aravind Ramamoorthy ◽  
Shapna Pal
Keyword(s):  
Electronic Packaging ◽  
Flip Chip ◽  
Failure Modes ◽  
Electronic Devices ◽  
Electrical Performance ◽  
Variable Frequency ◽  
Operating Parameters ◽  
Radiation Stress ◽  
Convection Oven ◽  
Electrical Degradation

This paper summarizes the effects of the variable frequency microwave (VFM) technique for rapid cure of polymeric encapsulants (such as flip-chip underfills) on the performance and reliability of electronic devices. Initial electrical performance of selected commercial IC packages following the application of VFM radiation stress has been recorded, and the performance has been compared to packages that were treated with comparable temperature cycles as applied in a convection oven. Failure analysis was performed on packages that showed electrical degradation to identify likely degradation and failure modes of the packaged ICs. Overall, our results show that VFM technology can safely be applied as an electronic packaging technology. However, proper control of VFM operating parameters is needed to ensure favorable performance of electronic devices.

Underfill Assessments and Validations for Low-k FCBGA

2006 ◽  
Author(s):  
Nicholas Kao ◽  
Jeng Yuan Lai ◽  
Jase Jiang ◽  
Yu Po Wang ◽  
C. S. Hsiao
Keyword(s):  
Finite Element ◽  
High Speed ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Material Selection ◽  
Coefficient Of Thermal Expansion ◽  
Electrical Performance ◽  
Low K ◽  
Underfill Material

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more I/Os signals and better electrical characteristics under same package form factor. Thus, Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pins accommodation and high transmission speed. For high-speed application, the low dielectric constant (low-k) material that can effectively reduce the signal delays is extensively used in IC chips. However, the low-k material possesses fragile mechanical property and high coefficient of thermal expansion (CTE) compared with silicon chip, which raises the reliability concerns of low-k material integrated into IC chip. The typical reliability failure modes are low-k layer delamination and bump crack under temperature loading during assembly and reliability test. Delamination is occurred in the interface between low-k dielectric layers and underfill material at chip corner. Bump crack is at Under Bump Metallization (UBM) corner. Thus, the adequate underfill material selection becomes very important for both solder bump and low-k chips [1]. This paper mainly characterized FCBGA underfill materials to guide the adequate candidates to prevent failures on low-k chip and solder bump. Firstly, test vehicle was a FCBGA package with heat spreader and was investigated the thermal stress by finite element models. In order to analyze localized low-k structures, sub-modeling technique is used for underfill characterizations. Then, the proper underfill candidates picked from modeling results were experimentally validated by reliability tests. Finally, various low-k FCBGA package structures were also studied with same finite element technique.

Development of Reliable Electronic Packaging Solutions for Spacecraft Avionics Miniaturization Using Embedded Passive Devices

2003 ◽  
Author(s):  
Don Schatzel
Keyword(s):  
Thin Film ◽  
Thermal Cycling ◽  
Electronic Packaging ◽  
Flip Chip ◽  
Dielectric Materials ◽  
Electrical Performance ◽  
Passive Devices ◽  
Die Attach ◽  
Space Environments ◽  
Viable Approach

Miniaturization of electronic packages will play a key role in future space avionics systems. Smaller avionics packages will reduce payloads while providing greater functionality for information processing and mission instrumentation. Current surface mount technology discrete passive devices not only take up significant space but also add weight. To that end, the use of embedded passive devices, such as capacitors, inductors and resistors will be instrumental in allowing electronics to be made smaller and lighter. Embedded passive devices fabricated on silicon or like substrates using thin film technology, promise great savings in circuit volume, as well as potentially improving electrical performance by decreasing parasitic losses. These devices exhibit a low physical profile and allow the circuit footprint to be reduced by stacking passive elements within a substrate. Thin film technologies used to deposit embedded passive devices are improving and costs associated with the process are decreasing. There are still many challenges with regard to this approach that must be overcome. In order to become a viable approach these devices need to work in conjunction with other active devices such as bumped die (flip chip) that share the same substrate area. This dictates that the embedded passive devices are resistant to the subsequent assembly processes associated with die attach (temperature, pressure). Bare die will need to be mounted directly on top of one or more layers of embedded passive devices. Currently there is not an abundant amount of information available on the reliability of these devices when subjected to the high temperatures of die attach or environmental thermal cycling for space environments. Device performance must be consistent over time and temperature with minimal parasitic loss. Pretested and assembled silicon substrates with layers of embedded capacitors made with two different dielectric materials, Ta2O5 (Tantalum Oxide) and benzocyclobutene (BCB), were subjected to the die attach process and tested for performance in an ambient environment. These assemblies were subjected to environmental thermal cycling from −55°C to 100°C. Preliminary results indicate embedded passive capacitors and resistors can fulfill the performance and reliability requirements of space flight on future missions. Testing results are encouraging for continued development of integrating embedded passive devices to replace conventional electronic packaging methods.

Variable Frequency Microwave Processing of Underfill Encapsulants for Flip-Chip Applications

2003 ◽  
Vol 125 (2) ◽  
pp. 302-307 ◽  
Author(s):  
Patricia F. Mead ◽  
Aravind Ramamoorthy ◽  
Shapna Pal ◽  
Z. Fathi ◽  
I. Ahmad
Keyword(s):  
Flip Chip ◽  
Microwave Processing ◽  
Variable Frequency ◽  
Particle Settling ◽  
Convection Oven ◽  
Innovative Technique ◽  
Cure Time ◽  
Underfill Encapsulant ◽  
Rapid Cure

This paper discusses an innovative technique for rapid cure of polymeric encapsulants such as underfills used in direct chip attach devices using variable frequency microwaves (VFM). VFM processing reduces the cure time for underfill encapsulants to 10 min or less, as compared to 30 or more minutes when using convection oven methods. We report here the results of our investigations measuring key material attributes of VFM and conventionally cured underfill encapsulant samples, and we also have characterized voiding and delamination characteristics of flip-chip with underfill test structures. Finally, particle settling in the flip-chip with underfill test structures has been characterized. Our results show that the VFM technique produces underfill attributes that are comparable to conventionally cured samples.

Rapid Cure Of Liquid Encapsulants And Structural Adhesives For Electronics Packaging Using Variable Frequency Microwave (Vfm) Energy

1996 ◽  
Vol 445 ◽  
Author(s):  
Zak Fathi ◽  
Denise A. Tucker ◽  
Billy J. Wei ◽  
Richard S. Garard ◽  
Patricia F. Mead ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Electronic Packaging ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Acoustic Microscopy ◽  
Variable Frequency ◽  
Scanning Calorimetry ◽  
Cycle Times ◽  
Process Technique ◽  
Field Uniformity

AbstractThis paper reports on the use of an emerging process technique for curing of polymer encapsulants as used in the electronic packaging industry. Previous work performed in the area of materials processing has demonstrated the usefulness of sweeping operating frequencies in order to achieve high levels of electric field uniformity and process control. The use of controlled variable frequency microwave energy has been evaluated as a process technique compatible with electronic packaging requirements. The heating of a series of integrated circuits (ICs) and their subsequent characterization was performed. IC integrity was investigated using X‐Ray, Acoustic Microscopy, Decapsulation and Bond Pull. Processing of liquid encapsulants, underfills and glob‐tops, used in Flip Chip and Chip On Board (COB) applications, was performed. Differential Scanning Calorimetry was used to study cure extent. Further studies show that variable frequency microwave processing leads to fast curing of encapsulants. A reduction in cycle times from 15 to 20 times over conventional curing has been observed. Also, results have showed a reduction in the stresses induced by mismatches in coefficient of thermal expansion.

Case Studies of Brittle Interfacial Failures in Area Array Solder Interconnects

2000 ◽  
Author(s):  
George M. Wenger ◽  
Richard J. Coyle ◽  
Patrick P. Solan ◽  
John K. Dorey ◽  
Courtney V. Dodd ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Failure Modes ◽  
Electroless Nickel ◽  
Electrical Performance ◽  
Printed Wiring Board ◽  
Solder Interconnects ◽  
Area Array ◽  
Surface Finishes ◽  
Soldering Reaction

Abstract A common pad finish on area array (BGA or CSP) packages and printed wiring board (PWB) substrates is Ni/Au, using either electrolytic or electroless deposition processes. Although both Ni/Au processes provide flat, solderable surface finishes, there are an increasing number of applications of the electroless nickel/immersion gold (ENi/IAu) surface finish in response to requirements for increased density and electrical performance. This increasing usage continues despite mounting evidence that Ni/Au causes or contributes to catastrophic, brittle, interfacial solder joint fractures. These brittle, interfacial fractures occur early in service or can be generated under a variety of laboratory testing conditions including thermal cycling (premature failures), isothermal aging (high temperature storage), and mechanical testing. There are major initiatives by electronics industry consortia as well as research by individual companies to eliminate these fracture phenomena. Despite these efforts, interfacial fractures associated with Ni/Au surface finishes continue to be reported and specific failure mechanisms and root cause of these failures remains under investigation. Failure analysis techniques and methodologies are crucial to advancing the understanding of these phenomena. In this study, the scope of the fracture problem is illustrated using three failure analysis case studies of brittle interfacial fractures in area array solder interconnects. Two distinct failure modes are associated with Ni/Au surface finishes. In both modes, the fracture surfaces appear to be relatively flat with little evidence of plastic deformation. Detailed metallography, scanning electron microscopy (SEM), energy dispersive x-ray analysis (EDX), and an understanding of the metallurgy of the soldering reaction are required to avoid misinterpreting the failure modes.

Focused Ion Beam Irradiation Induced Damages on CMOS and Bipolar Technologies

1998 ◽  
Author(s):  
J. Benbrik ◽  
G. Rolland ◽  
P. Perdu ◽  
B. Benteo ◽  
M. Casari ◽  
...  
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Electronic Devices ◽  
Complete Characterization ◽  
Bipolar Transistors ◽  
Ion Beam Irradiation ◽  
Physical Mechanisms ◽  
Dc Characteristics ◽  
Electrical Degradation ◽  
Physical Phenomena

Abstract Focused Ion Beam is commonly used for IC repairs and modifications. However, FIB operation may also induce a damaging impact which can takes place far from the working area due to the charge-up phenomenon. A complete characterization joined to an in-depth understanding of the physical phenomena arising from FIB irradiation is therefore necessary to take into account spurious FIB induced effects and to enhance the success of FIB modifications. In this paper, we present the effects of FIB irradiation on the electrical DC performances of different electronic devices such as nMOS and pMOS transistors, CMOS inverters, PN junctions and bipolar transistors. From the observed behavior of the DC characteristics evolution of the devices, some suggestions about physical mechanisms inducing the electrical degradation are proposed.

Microhardness Testing on Via Fill Material for Via In Pad Technology

2003 ◽  
Author(s):  
Norman J. Armendariz ◽  
Carolyn McCormick
Keyword(s):  
Printed Circuit Board ◽  
Failure Modes ◽  
Strong Dependence ◽  
Circuit Board ◽  
Electrical Performance ◽  
Gravimetric Analysis ◽  
Passive Components ◽  
Root Cause ◽  
Fill Material ◽  
Signal Routing

Abstract Via in pad PCB (Printed Circuit board) technology for passive components such as chip capacitors and resistors, provides the potential for improved signal routing density and reduced PCB area. Because of these improvements there is the potential for PCB cost reduction as well as gains in electrical performance through reduced impedance and inductance. However, not long after the implementation, double digit unit failures for solder joint electrical opens due to capacitor “tombstoning” began to occur. Failure modes included via fill material (solder mask) protrusion from the via as well as “out gassing” and related “tombstoning.” This failure analysis involved investigating a strong dependence on PCB supplier and, less obviously, manufacturing site. Other factors evaluated included via fill material, drill size, via fill thermal history and via fill amount or fill percent. The factor most implicated was incomplete cure of the via fill material. Previous thermal gravimetric analysis methods to determine level of polymerization or cure did not provide an ability to measure and demonstrate via fill cure level in small selected areas or its link to the failures. As a result, there was a metrology approach developed to establish this link and root-cause the failures in the field, which was based on microhardness techniques and noncontact via fill measuring metrologies.

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