Rapid Cure Of Liquid Encapsulants And Structural Adhesives For Electronics Packaging Using Variable Frequency Microwave (Vfm) Energy

1996 ◽  
Vol 445 ◽  
Author(s):  
Zak Fathi ◽  
Denise A. Tucker ◽  
Billy J. Wei ◽  
Richard S. Garard ◽  
Patricia F. Mead ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Electronic Packaging ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Acoustic Microscopy ◽  
Variable Frequency ◽  
Scanning Calorimetry ◽  
Cycle Times ◽  
Process Technique ◽  
Field Uniformity

AbstractThis paper reports on the use of an emerging process technique for curing of polymer encapsulants as used in the electronic packaging industry. Previous work performed in the area of materials processing has demonstrated the usefulness of sweeping operating frequencies in order to achieve high levels of electric field uniformity and process control. The use of controlled variable frequency microwave energy has been evaluated as a process technique compatible with electronic packaging requirements. The heating of a series of integrated circuits (ICs) and their subsequent characterization was performed. IC integrity was investigated using X‐Ray, Acoustic Microscopy, Decapsulation and Bond Pull. Processing of liquid encapsulants, underfills and glob‐tops, used in Flip Chip and Chip On Board (COB) applications, was performed. Differential Scanning Calorimetry was used to study cure extent. Further studies show that variable frequency microwave processing leads to fast curing of encapsulants. A reduction in cycle times from 15 to 20 times over conventional curing has been observed. Also, results have showed a reduction in the stresses induced by mismatches in coefficient of thermal expansion.

Interactions between Variable Frequency Microwave Underfill Processing and High Performance Packaging Materials

2013 ◽  
Vol 2013 (1) ◽  
pp. 000461-000466 ◽  
Author(s):  
Mamadou Diobet Diop ◽  
Marie-Claude Paquet ◽  
Dominique Drouin ◽  
David Danovitch
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Curing Temperature ◽  
Variable Frequency ◽  
Asymmetric Distribution ◽  
Unexpected Result ◽  
Scanning Calorimetry ◽  
Negative Effect ◽  
Curing Methods

Variable frequency microwave (VFM) has been recently proposed as an alternative underfill curing method that provides flip chip package warpage improvement as well as potential underfill cure time reductions. The current paper outlines how such advantages in VFM processing of underfill can be compromised when applied to high performance organic packages. VFM recipes for three underfill materials were developed by performing several VFM curing runs followed by curing rate measurements using the differential scanning calorimetry method. The VFM curing rate was seen to strongly dependent upon the underfill chemistry. By testing flip chip parts that comprised large and high-end substrates, we showed that the underfill material has negligible impact on VFM warpage with the major cause attributed to the coefficient of thermal expansion mismatch between the die and the substrate. Comparison between the convection and the VFM methods indicated two warpage tendencies that depended upon the VFM curing temperature. First, when both curing methods used comparably high temperatures, warpage increases up to about + 20% were found with VFM. This unexpected result was explained by the high-density Cu loading of the substrate which systematically carried heat generated by VFM energy from the die/underfill system to the substrate. Since this high-end substrate consists of sequential dielectric/Cu layers with asymmetric distribution of Cu, additional stresses due to local CTE mismatches between the Cu and the dielectric layers were induced within the substrate processed with VFM. Second, warpage reductions down to about − 22% were obtained at the VFM curing temperature of 110°C with a curing time similar to that of convection cure. This suggests that the negative effect of the local CTE mismatches were no longer at play at the lower VFM temperatures and that the significantly lower final cure temperatures produced lower total shrinkage of the die and the substrate. Finally, due to lower elastic moduli, the cured VFM parts showed better mechanical reliability with no fails up to 1500 cycles.

Thin Film Multichip Packaging for High Temperature Digital Electronics

2011 ◽  
Vol 2011 (HITEN) ◽  
pp. 000039-000045 ◽  
Author(s):  
Kun Fang ◽  
Rui Zhang ◽  
Tami Isaacs-Smith ◽  
R. Wayne Johnson ◽  
Emad Andarawis ◽  
...  
Keyword(s):  
Thin Film ◽  
High Temperature ◽  
Integrated Circuits ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Electrical Characteristics ◽  
Passive Components ◽  
Interlayer Dielectric ◽  
Base Ceramic ◽  
Film Substrate

Digital silicon carbide integrated circuits provide enhanced functionality for electronics in geothermal, aircraft and other high temperature applications. A multilayer thin film substrate technology has been developed to interconnect multiple SiC devices along with passive components. The conductor is vacuum deposited Ti/Ti:W/Au followed by an electroplated Au. A PECVD silicon nitride is used for the interlayer dielectric. Adhesion testing of the conductor and the dielectric was performed as deposited and after aging at 320°C. The electrical characteristics of the dielectric as a function of temperature were measured. Thermocompression flip chip bonding of Au stud bumped SiC die was used for electrical connection of the digital die to the thin film substrate metallization. Since polymer underfills are not compatible with 300°C operation, AlN was used as the base ceramic substrate to minimize the coefficient of thermal expansion mismatch between the SiC die and the substrate. Initial die shear results are presented.

Investigation of Variable Frequency Microwave Processing for Electronic Packaging Applications

2003 ◽  
Vol 125 (2) ◽  
pp. 294-301 ◽  
Author(s):  
Patricia F. Mead ◽  
Aravind Ramamoorthy ◽  
Shapna Pal
Keyword(s):  
Electronic Packaging ◽  
Flip Chip ◽  
Failure Modes ◽  
Electronic Devices ◽  
Electrical Performance ◽  
Variable Frequency ◽  
Operating Parameters ◽  
Radiation Stress ◽  
Convection Oven ◽  
Electrical Degradation

This paper summarizes the effects of the variable frequency microwave (VFM) technique for rapid cure of polymeric encapsulants (such as flip-chip underfills) on the performance and reliability of electronic devices. Initial electrical performance of selected commercial IC packages following the application of VFM radiation stress has been recorded, and the performance has been compared to packages that were treated with comparable temperature cycles as applied in a convection oven. Failure analysis was performed on packages that showed electrical degradation to identify likely degradation and failure modes of the packaged ICs. Overall, our results show that VFM technology can safely be applied as an electronic packaging technology. However, proper control of VFM operating parameters is needed to ensure favorable performance of electronic devices.

Warpage Analysis of Underfilled Wafers

2004 ◽  
Vol 126 (2) ◽  
pp. 265-270 ◽  
Author(s):  
Hai Ding ◽  
I. Charles Ume ◽  
Cheng Zhang
Keyword(s):  
Young’S Modulus ◽  
Electronic Packaging ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Young's Modulus ◽  
Wafer Level ◽  
Element Analysis ◽  
Low Temperature Storage ◽  
Shadow Moire ◽  
Shadow Moiré

Wafer-level packaging (WLP) is one of the future trends in electronic packaging. Since 1994, many companies have released various WLP licenses. One of the common concerns of WLP is wafer warpage. Warpage of wafers tends to introduce cracking or delamination during dicing and low temperature storage processes. After wafer dicing, warpage could affect the quality of the dies and shorten the life of each packaged product. Many documented works indicated that in the design and implementation of multilayer structured electronic packaging products, some key parameters must be carefully considered and closely controlled to ensure the best packaging quality with the minimum warpage. During the wafer-level flip chip assembly process, the application of underfill on the whole wafer is a critical step. In this step, the key underfill parameters that affect wafer warpage are Young’s modulus, thickness, and coefficient of thermal expansion (CTE). In this paper, an experimental design and statistical methods were used to identify the model structure and parameters that are critical to the warpage of wafers. Bilinear regression models were identified based on the data obtained from finite element analysis (FEA) that was verified by shadow moire´ experiments. In FEA, the underfilled wafer structure is simplified to consisting of two layers of linear elastic materials. According to the models, the CTE, the coupling of Young’s modulus and CTE, and the coupling of thickness and CTE primarily determine wafer warpage. Further FEA and shadow moire´ experiments indicate that the models are capable of predicting wafer warpage in the WLP processes.

Failure Analysis of Flip-Chip Interconnections Through Acoustic Microscopy

1996 ◽  
Author(s):  
O. Diaz de Leon ◽  
M. Nassirian ◽  
C. Todd ◽  
R. Chowdhury
Keyword(s):  
Failure Analysis ◽  
Large Scale ◽  
Flip Chip ◽  
Ultrasonic Waves ◽  
Acoustic Microscopy ◽  
Acoustic Microscope ◽  
Chip Technology ◽  
Ball Joints ◽  
Non Destructive ◽  
Scanning Acoustic Microscope

Abstract Integration of circuits on semiconductor devices with resulting increase in pin counts is driving the need for improvements in packaging for functionality and reliability. One solution to this demand is the Flip- Chip concept in Ultra Large Scale Integration (ULSI) applications [1]. The flip-chip technology is based on the direct attach principle of die to substrate interconnection.. The absence of bondwires clearly enables packages to become more slim and compact, and also provides higher pin counts and higher-speeds [2]. However, due to its construction, with inherent hidden structures the Flip-Chip technology presents a challenge for non-destructive Failure Analysis (F/A). The scanning acoustic microscope (SAM) has recently emerged as a valuable evaluation tool for this purpose [3]. C-mode scanning acoustic microscope (C-SAM), has the ability to demonstrate non-destructive package analysis while imaging the internal features of this package. Ultrasonic waves are very sensitive, particularly when they encounter density variations at surfaces, e.g. variations such as voids or delaminations similar to air gaps. These two anomalies are common to flip-chips. The primary issue with this package technology is the non-uniformity of the die attach through solder ball joints and epoxy underfill. The ball joints also present defects as open contacts, voids or cracks. In our acoustic microscopy study packages with known defects are considered. It includes C-SCAN analysis giving top views at a particular package interface and a B-SCAN analysis that provides cross-sectional views at a desired point of interest. The cross-section analysis capability gives confidence to the failure analyst in obtaining information from a failing area without physically sectioning the sample and destroying its electrical integrity. Our results presented here prove that appropriate selection of acoustic scanning modes and frequency parameters leads to good reliable correlation between the physical defects in the devices and the information given by the acoustic microscope.

Extending Acoustic Microscopy for Comprehensive Failure Analysis Applications

2010 ◽  
Author(s):  
Sebastian Brand ◽  
Matthias Petzold ◽  
Peter Czurratis ◽  
Peter Hoffrogge
Keyword(s):  
Image Processing ◽  
Failure Analysis ◽  
Signal Analysis ◽  
Flip Chip ◽  
Fault Isolation ◽  
Acoustic Microscopy ◽  
Specific Information ◽  
Full Potential ◽  
Time Frequency ◽  
Non Destructive

Abstract In industrial manufacturing of microelectronic components, non-destructive failure analysis methods are required for either quality control or for providing a rapid fault isolation and defect localization prior to detailed investigations requiring target preparation. Scanning acoustic microscopy (SAM) is a powerful tool enabling the inspection of internal structures in optically opaque materials non-destructively. In addition, depth specific information can be employed for two- and three-dimensional internal imaging without the need of time consuming tomographic scan procedures. The resolution achievable by acoustic microscopy is depending on parameters of both the test equipment and the sample under investigation. However, if applying acoustic microscopy for pure intensity imaging most of its potential remains unused. The aim of the current work was the development of a comprehensive analysis toolbox for extending the application of SAM by employing its full potential. Thus, typical case examples representing different fields of application were considered ranging from high density interconnect flip-chip devices over wafer-bonded components to solder tape connectors of a photovoltaic (PV) solar panel. The progress achieved during this work can be split into three categories: Signal Analysis and Parametric Imaging (SA-PI), Signal Analysis and Defect Evaluation (SA-DE) and Image Processing and Resolution Enhancement (IP-RE). Data acquisition was performed using a commercially available scanning acoustic microscope equipped with several ultrasonic transducers covering the frequency range from 15 MHz to 175 MHz. The acoustic data recorded were subjected to sophisticated algorithms operating in time-, frequency- and spatial domain for performing signal- and image analysis. In all three of the presented applications acoustic microscopy combined with signal- and image processing algorithms proved to be a powerful tool for non-destructive inspection.

Enhancements of Non-contact Measurements of Electrical Waveforms on the Proximity of a Signal Surface Using Groups of Pulses

2002 ◽  
Author(s):  
Fenglei Du ◽  
Greg Bridges ◽  
D.J. Thomson ◽  
Rama R. Goruganthu ◽  
Shawn McBride ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Signal To Noise Ratio ◽  
Electrostatic Force ◽  
Single Pulse ◽  
Electric Signal ◽  
Measurement Instruments ◽  
Cycle Times ◽  
Force Microscopy ◽  
And Performance

Abstract With the ever-increasing density and performance of integrated circuits, non-invasive, accurate, and high spatial and temporal resolution electric signal measurement instruments hold the key to performing successful diagnostics and failure analysis. Sampled electrostatic force microscopy (EFM) has the potential for such applications. It provides a noninvasive approach to measuring high frequency internal integrated circuit signals. Previous EFMs operate using a repetitive single-pulse sampling approach and are inherently subject to the signal-to-noise ratio (SNR) problems when test pattern duty cycle times become large. In this paper we present an innovative technique that uses groups of pulses to improve the SNR of sampled EFM systems. The approach can easily provide more than an order-ofmagnitude improvement to the SNR. The details of the approach are presented.

Effects of Backside Circuit Edit on Transistor Characteristics

2007 ◽  
Author(s):  
R.K. Jain ◽  
T. Malik ◽  
T.R. Lundquist ◽  
Q.S. Wang ◽  
R. Schlangen ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flip Chip ◽  
Intrinsic Parameters ◽  
Chip Type ◽  
Device Structures ◽  
Before And After ◽  
Silicon Device ◽  
Metal Layers

Abstract Backside circuit edit techniques on integrated circuits (ICs) are becoming common due to increase number of metal layers and flip chip type packaging. However, a thorough study of the effects of these modifications has not been published. This in spite of the fact that the IC engineers have sometimes wondered about the effects of backside circuit edit on IC behavior. The IC industry was well aware that modifications can lead to an alteration of the intrinsic behavior of a circuit after a FIB edit [1]. However, because alterations can be controlled [2], they have not stopped the IC industry from using the FIB to successfully reconfigure ICs to produce working “silicon” to prove design and mask changes. Reliability of silicon device structures, transistors and diodes, are investigated by monitoring intrinsic parameters before and after various steps of modification.

Failure Analysis of Short Faults on Advanced Wire-Bond and Flip-Chip Packages with Scanning SQUID Microscopy

2004 ◽  
Author(s):  
Steve K. Hsiung ◽  
Kevan V. Tan ◽  
Andrew J. Komrowski ◽  
Daniel J. D. Sullivan ◽  
Jan Gaudestad
Keyword(s):  
Magnetic Fields ◽  
Integrated Circuits ◽  
Quantum Interference ◽  
Flip Chip ◽  
Infrared Emission ◽  
Fault Analysis ◽  
Wire Bond ◽  
Overlay Design ◽  
Scanning Squid ◽  
Metal Layers

Abstract Scanning SQUID (Superconducting Quantum Interference Device) Microscopy, known as SSM, is a non-destructive technique that detects magnetic fields in Integrated Circuits (IC). The magnetic field, when converted to current density via Fast Fourier Transform (FFT), is particularly useful to detect shorts and high resistance (HR) defects. A short between two wires or layers will cause the current to diverge from the path the designer intended. An analyst can see where the current is not matching the design, thereby easily localizing the fault. Many defects occur between or under metal layers that make it impossible using visible light or infrared emission detecting equipment to locate the defect. SSM is the only tool that can detect signals from defects under metal layers, since magnetic fields are not affected by them. New analysis software makes it possible for the analyst to overlay design layouts, such as CAD Knights, directly onto the current paths found by the SSM. In this paper, we present four case studies where SSM successfully localized short faults in advanced wire-bond and flip-chip packages after other fault analysis methods failed to locate the defects.

Magnetic Current Imaging Techniques: Comparative Case Studies

2004 ◽  
Author(s):  
Olivier Crépel ◽  
Philippe Descamps ◽  
Patrick Poirier ◽  
Romain Desplats ◽  
Philippe Perdu ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Integrated Circuits ◽  
Case Studies ◽  
Flip Chip ◽  
Imaging Techniques ◽  
Optimal Domain ◽  
Magnetic Current ◽  
Comparative Case Studies ◽  
Current Flows

Abstract Magnetic field based techniques have shown great capabilities for investigation of current flows in integrated circuits (ICs). After reviewing the performances of SQUID, GMR (hard disk head technologies) and MTJ existing sensors, we will present results obtained on various case studies. This comparison will show the benefit of each approach according to each case study (packaged devices, flip-chip circuits, …). Finally we will discuss on the obtained results to classify current techniques, optimal domain of applications and advantages.

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