Reliability of Anisotropically Conductive Adhesive Joints on a Flip-Chip/FR-4 Substrate

2002 ◽  
Vol 124 (3) ◽  
pp. 240-245 ◽  
Author(s):  
Johan Liu ◽  
Zonghe Lai
Keyword(s):  
Flip Chip ◽  
High Reliability ◽  
Low Cost ◽  
Adhesive Joints ◽  
Temperature Cycling ◽  
Conductive Adhesive ◽  
Resistance Measurement ◽  
Time To Failure ◽  
Low Cost Substrate

A reliability study on anisotropically conductive adhesive joints on a Flip-Chip/FR-4 assembly has been carried out. In the study, nine types of anisotropic conductive adhesive (ACA) and one nonconductive film (NCF) were used. In total, nearly one-thousand single joints were subjected to reliability tests in terms of temperature cycling between −40°C and 125°C with a dwell time of 15 minutes and a ramp rate of 110°C/min. The test chip used for this extensive reliability test had a pitch of 100 μm. Therefore, this work was particularly focused on evaluation on the reliability of ultra fine pitch flip-chip interconnections using anisotropically conductive adhesives on a low-cost substrate. The reliability was characterized by single contact resistance measurement using the four-probe method during temperature cycling testing up to 3000 cycles. The Mean Time To Failure (MTTF) (defined as 50% failure of all tested joints) are 650, 2500, and 3500 cycles when the failure definition is defined as 20% increase, larger than 50 mΩ and larger than 100 mΩ, respectively, using the in-situ electrical resistance measurement technique. Using the discontinuous (manual) measurement at room temperature by taking out the sample from the cycling chamber, the MTTF for the same joint system is around 2500 cycles in the case that the failure criteria is defined as 20% of the resistance increase, far better than the results from the in-situ measurement. The results show clearly that in optimized conditions, high reliability flip-chip anisotropically conductive adhesive joints on low-cost substrate can be achieved.

High Reliability Flip Chip Using Low CTE Laminate Substrates

2005 ◽  
Author(s):  
D. Scott Copeland ◽  
M. Kaysar Rahim ◽  
Jeffrey C. Suhling ◽  
Guoyun Tian ◽  
Pradeep Lall ◽  
...  
Keyword(s):  
Carbon Fiber ◽  
Thermal Cycling ◽  
Flip Chip ◽  
Experimental Testing ◽  
High Reliability ◽  
Low Cost ◽  
Substrate Material ◽  
Space Applications ◽  
Sandwich Construction ◽  
Test Chips

In this work, we report on our efforts to develop high reliability flip chip on laminate assemblies for deployment in harsh thermal cycling environments characteristic of ground and aerospace vehicles (e.g. −55 to 150 °C). Reliability enhancement has been achieved through the use of a novel low expansion, high stiffness, and relatively low cost laminate substrate material that virtually eliminates CTE mismatches between the silicon die and top layer PCB interconnect. The utilized laminate features a sandwich construction that contains standard FR-406 outer layers surrounding a low expansion high thermal conductivity carbon fiber-reinforced composite core (STABLCOR®). Through both experimental testing and modeling, we have demonstrated that robust flip chip assemblies can be produced that illustrate ultra-high solder joint reliability during thermal cycling and extremely low die stresses. Liquid to liquid thermal shock testing has been performed on test assemblies incorporating daisy chain test die, and piezoresistive test chips have been used to characterize temperature dependent die stresses. In both sets of experiments, results obtained using the hybrid PCB laminate with FR-406 outer layers and carbon fiber core have been compared to those obtained with more traditional glass-epoxy laminate substrates including FR-406 and NELCO 4000-13. Nonlinear finite element modeling results for the low expansion flip chip on laminate assemblies have been correlated with the experimental data. Unconstrained thermal expansion measurements have also been performed on the hybrid laminate materials using strain gages to demonstrate their low CTE characteristics. Other experimental testing has demonstrated that the new laminate successfully passes toxicity, flammability, and vacuum stability testing as required for pressurized and un-pressurized space applications.

Mechanical and Thermal Board Level Reliability Comparison Between Electroless Ni Im. Au and Solder on Pad Surface Finishes for Large Flip Chip BGA Packages

2006 ◽  
Author(s):  
Gnyaneshwar Ramakrishna ◽  
Donghyun Kim ◽  
Mudasir Ahamad ◽  
Lavanya Gopalakrishnan ◽  
Mason Hu ◽  
...  
Keyword(s):  
Surface Finish ◽  
Flip Chip ◽  
High Reliability ◽  
Electroless Nickel ◽  
Temperature Cycling ◽  
Design Parameters ◽  
Temperature Cycle ◽  
Bga Packages ◽  
Reliability And Robustness ◽  
Board Level

Large Flip Chip BGA (FCBGA) packages are needed in high pin out applications (>1800), e.g., ASIC's and are typically used in high reliability and robustness applications. Hence understanding the package reliability and robustness becomes one of paramount importance for efficient product design. There are various aspects to the package that need to be understood, to ensure an effective design. The focus of this paper is to understand the BGA reliability of the package with particular reference to comparison of the surface finish, vis-a`-vis, between Electroless Nickel Immersion Gold (ENIG) and Solder On Pad (SOP) on the substrate side of the package, which are the typical solutions for large plastic FC-BGA packages. Tests, which include board level temperature cycling, monotonic bend and shock testing have been conducted to compare the two surface finish options. The results of these tests demonstrate that the mechanical strength of the interface exceeds by a factor of two for the SOP surface finish, while BGA design parameters play a key role in ensuring comparative temperature cycle reliability in comparison with ENIG packages.

High Reliability Underfill for Flip-Chip Application

1996 ◽  
Vol 445 ◽  
Author(s):  
K. Sumita ◽  
K. Kumagae ◽  
K. Dobashi ◽  
T. Shiobara ◽  
M. Kuroda
Keyword(s):  
Ring Opening ◽  
Flip Chip ◽  
High Reliability ◽  
Void Formation ◽  
Ring Opening Polymerization ◽  
Organic Substrate ◽  
Temperature Cycling ◽  
Excellent Adhesion ◽  
Reliability Performance ◽  
Modified Epoxy

AbstractA new underfill was developed for a flip chip application with a large VLSI die. The new underfill is resistant to hydrolysis, exhibits a significantly lower moisture saturation level than widely used carboxylic anhydride cured underfills, demonstrates superb penetration capability between such a large die and an organic substrate without void formation, and delivers excellent adhesion characteristics and reliability performance during temperature cycling test and PCT (pressure cooker test).The new underfill utilizes amine catalyzed ring opening polymerization of epoxides, forms ether linkages during cure rather than ester linkages which anhydride cured underfills form, and strongly resists to hydrolysis. The underfill is less sensitive to moisture contamination and provides improved floor life as well as storage life in contrast to anhydride cured underfills as well. Unique low stress performance and penetration capability of the underfill are attributed to the use of proprietary silicone modified epoxy resin as well as highly loaded filler of optimized size, shape and size distribution in reference to the gap between a die and an organic substrate.An optimum cure schedule and a desirable viscosity range have also been identified for the new underfill to minimize filler segregation. Proper preheating of a die‐substrate has effectively reduced void formation while facilitating the removal of volatile from an organic substrate.

Die Stress Variation During Thermal Cycling Reliability Tests

2007 ◽  
Author(s):  
M. Kaysar Rahim ◽  
Jordan Roberts ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
Pradeep Lall
Keyword(s):  
Thermal Cycling ◽  
Electronic Packaging ◽  
Room Temperature ◽  
Flip Chip ◽  
Constitutive Relations ◽  
Temperature Cycling ◽  
Material Behavior ◽  
Aging Effects ◽  
Test Chips

Thermal cycling accelerated life testing is an established technique for thermo-mechanical evaluation and qualification of electronic packages. Finite element life predictions for thermal cycling configurations are challenging due to several reasons including the complicated temperature/time dependent constitutive relations and failure criteria needed for solders, encapsulants and their interfaces; aging/evolving material behavior for the packaging materials (e.g. solders); difficulties in modeling plating finishes; the complicated geometries of typical electronic assemblies; etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling are difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, little is known about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In this work, we have used test chips containing piezoresistive stress sensors to characterize the in-situ die surface stress during long-term thermal cycling of electronic packaging assemblies. Using (111) silicon test chips, the complete three-dimensional stress state (all 6 stress components) was measured at each rosette site by monitoring the resistance changes occurring in the sensors. The packaging configuration studied in this work was flip chip on laminate where 5 × 5 mm perimeter bumped die were assembled on FR-406 substrates. Three different thermal cycling temperature profiles were considered. In each case, the die stresses were initially measured at room temperature after packaging. The packaged assemblies were then subjected to thermal cycling and measurements were made either incrementally or continuously during the environmental exposures. In the incremental measurements, the packages were removed from the chamber after various durations of thermal cycling (e.g. 250, 500, 750, 1000 cycles, etc.), and the sensor resistances were measured at room temperature. In the continuous measurements, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously during the thermal cycling exposure. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental observations show cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage.

scholarly journals NoCGuard: A Reliable Network-on-Chip Router Architecture

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 342 ◽  
Author(s):  
Muhammad Akmal Shafique ◽  
Naveed Khan Baloch ◽  
Muhammad Iram Baig ◽  
Fawad Hussain ◽  
Yousaf Bin Zikria ◽  
...  
Keyword(s):  
Network Architecture ◽  
Fault Tolerant ◽  
Channel Allocation ◽  
High Reliability ◽  
Low Cost ◽  
Network On Chip ◽  
Time To Failure ◽  
Protection Factor ◽  
Router Architecture ◽  
On Chip

Aggressive scaling in deep nanometer technology enables chip multiprocessor design facilitated by the communication-centric architecture provided by Network-on-Chip (NoC). At the same time, it brings considerable challenges in reliability because a fault in the network architecture severely impacts the performance of a system. To deal with these reliability challenges, this research proposed NoCGuard, a reconfigurable architecture designed to tolerate multiple permanent faults in each pipeline stage of the generic router. NoCGuard router architecture uses four highly reliable and low-cost fault-tolerant strategies. We exploited resource borrowing and double routing strategy for the routing computation stage, default winner strategy for the virtual channel allocation stage, runtime arbiter selection and default winner strategy for the switch allocation stage and multiple secondary bypass paths strategy for the crossbar stage. Unlike existing reliable router architectures, our architecture features less redundancy, more fault tolerance, and high reliability. Reliability comparison using Mean Time to Failure (MTTF) metric shows 5.53-time improvement in a lifetime and using Silicon Protection Factor (SPF), 22-time improvement, which is better than state-of-the-art reliable router architectures. Synthesis results using 15 nm and 45 nm technology library show that additional circuitry incurs an area overhead of 28.7% and 28% respectively. Latency analysis using synthetic, PARSEC and SPLASH-2 traffic shows minor increase in performance by 3.41%, 12% and 15% respectively while providing high reliability.

Sign in / Sign up

Export Citation Format

Share Document