Fracture Mechanics Analysis of Low Cost Solder Bumped Flip Chip Assemblies With Imperfect Underfills

2000 ◽  
Vol 122 (4) ◽  
pp. 306-310 ◽  
Author(s):  
John H. Lau ◽  
S.-W. Ricky Lee
Keyword(s):  
Fracture Mechanics ◽  
Solder Joint ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Low Cost ◽  
Strain Energy Release ◽  
Circuit Board ◽  
Temperature Dependent ◽  
Joint Reliability

Solder joint reliability of flip chip on various thickness of printed circuit board with imperfect underfill is presented in this study. Emphasis is placed on the determination of the temperature-dependent stress and plastic strain at the corner solder joint with different crack (delamination) lengths. Also, the strain energy release rate and phase angle at the crack tip of the interface between the underfill and solder mask are obtained by fracture mechanics. [S1043-7398(00)01104-X]

Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications

2002 ◽  
Vol 124 (3) ◽  
pp. 205-211 ◽  
Author(s):  
John H. Lau ◽  
S. W. Ricky Lee ◽  
Stephen H. Pan ◽  
Chris Chang
Keyword(s):  
Cross Sections ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Low Cost ◽  
Circuit Board ◽  
Test Results ◽  
Pcb Assembly ◽  
Creep Analysis ◽  
Chip Scale Package ◽  
Time Dependent Analysis

An elasto-plastic-creep analysis of a low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip in a chip scale package (CSP) format which is soldered onto a printed circuit board (PCB) is presented in this study. Emphasis is placed on the design, materials, and reliability of the micro VIP substrate and of the micro VIP CSP solder joints on PCB. The solder is assumed to obey Norton’s creep law. Cross-sections of samples are examined for a better understanding of the solder bump, CSP substrate redistribution, micro VIP, and solder joint. Also, the thermal cycling test results of the micro VIP CSP PCB assembly is presented.

scholarly journals Improving the Solder Joint Reliability of a Power Leadframe Package Using Thermomechanical Simulation

2019 ◽  
pp. 1-6
Author(s):  
Jefferson Talledo
Keyword(s):  
Solder Joint ◽  
Heat Dissipation ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Mold Material ◽  
Element Analysis ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Thermomechanical Simulation ◽  
Board Level

Leadframe-based packages are commonly used for semiconductor power devices. With these packages, heat dissipation is much better compared with laminate substrated-based packages. However, the solder joint reliability requirement under thermal cycling condition is also higher and this is what makes the development of a power package challenging. One of the usual requirements from customers is that there should be no solder joint failure up to 2,000 thermal cycles. This paper presents the thermomechanical simulation of a power leadframe package that was conducted to improve its solder joint reliability. Board level solder joint cycle life was predicted using finite element analysis and the result was validated with actual solder life result from board level reliability evaluation. Since available solder prediction equation was for the characteristic life (63.2% accumulative failure), using the normalized characteristic life was implemented for predicting the number of cycles to first failure of the solder joint connection and the approach showed good agreement with the actual result. Results also indicated that the choice of epoxy mold material and the type of PCB (printed circuit board) have a significant contribution to the solder joint reliability performance.

scholarly journals Study on the Impact of Lead Sidewall Solder Coverage and Corner Lead Size on Joint Reliability

2021 ◽  
pp. 62-69
Author(s):  
Jefferson Talledo
Keyword(s):  
Solder Joint ◽  
Integrated Circuit ◽  
High Speed ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Element Analysis ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Solder Fatigue ◽  
The Impact

Solder joint reliability is very important to ensure that an integrated circuit (IC) semiconductor package is functional within its intended life span as the solder joint establishes electrical connection between the IC and the printed circuit board (PCB). Solder fatigue failure or crack under thermal cycling is one of the common problems with board-mounted packages. There are several factors or package characteristics that have impact on solder fatigue life like package size and material properties of the package components. This paper presents a thermo-mechanical modeling of a leadframe-based semiconductor package to study the impact of lead sidewall solder coverage and corner lead size on the solder joint reliability. Finite element analysis (FEA) technique was used to calculate the solder life considering 50% and 100% package lead sidewall solder coverage as well as smaller and larger critical corner leads of the package. The results of the analysis showed that higher lead sidewall solder coverage and larger lead could significantly increase solder life. Therefore, ensuring lead sidewall solder wettability to have higher solder coverage is beneficial. The study also reveals that packages with side wettable flanks are not only enabling high speed automated optical inspection required for the automotive industry, but they are also providing improved solder joint reliability.

Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications

2000 ◽  
Author(s):  
John H. Lau ◽  
S. W. Ricky Lee ◽  
Stephen H. Pan ◽  
Chris Chang
Keyword(s):  
Cross Sections ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Low Cost ◽  
Circuit Board ◽  
Pcb Assembly ◽  
Creep Analysis ◽  
Chip Scale Package ◽  
Plastic Creep ◽  
Time Dependent Analysis

Abstract An elasto-plastic-creep analysis of a low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip in a chip scale package (CSP) format which is soldered onto a printed circuit board (PCB) is presented in this study. Emphasis is placed on the design, materials, and reliability of the micro VIP substrate and of the micro VIP CSP solder joints on PCB. The solder is assumed to obey Norton’s creep law. Cross-sections of samples are examined for a better understanding of the solder bump, CSP substrate redistribution, micro VIP, and solder joint. Also, the micro VIP CSP PCB assembly is subjected to thermal cycling tests.

Thermal Management in Direct Chip Attach Assemblies

1999 ◽  
Vol 121 (4) ◽  
pp. 222-230
Author(s):  
D. F. Baldwin ◽  
J. T. Beerensson
Keyword(s):  
Thermal Management ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Low Cost ◽  
Consumer Electronics ◽  
Thermal Design ◽  
Circuit Board ◽  
Thermal Dissipation ◽  
Experimental Measurements ◽  
Organic Substrates

Direct chip attach (DCA) packaging technologies are finding increasing application in electronics manufacturing particularly in telecommunications and consumer electronics. In these systems, bare die are interconnected directly to a printed circuit board. The two primary forms of DCA included chip on board (COB) where the die are attached face up and wirebonded to the substrate and flip chip on board (FCOB) where bumped die are interconnected active face down directly to low-cost organic substrates. In the current work, thermal management of four direct chip attach technologies is investigated. Experimental measurements are conducted exploring the junction-to-ambient thermal resistance and thermal dissipation paths for COB interconnection and three FCOB interconnect technologies including solder attach, anisotropic adhesive attach, and isotropic adhesive attach. A first-order chip-scale thermal design model is developed for flip chip assemblies exhibiting good agreement with the experimental measurements.

Controlling the Solder Joint Reliability of eWLB Packages in Automotive Radar Applications Using a Design for Reliability Approach

2018 ◽  
Author(s):  
M. Niessner ◽  
G. Haubner ◽  
W. Hartner ◽  
S. Pahlke
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Wafer Level ◽  
Automotive Radar ◽  
Low Loss ◽  
Solder Joint Reliability ◽  
Design For Reliability ◽  
Joint Reliability ◽  
Ball Grid Array Packages

A DfR (Design for Reliability) approach which is systematically based on simulation, sensitivity analysis and experimental validation is applied for identifying, understanding and controlling the key factors which determine the solder joint reliability of eWLB (Embedded Wafer Level Ball Grid Array) packages that carry embedded 77 GHz dies and sit on hybrid PCB (Printed Circuit Board) stacks. The hybrid stack investigated in this work is characteristic to automotive RADAR (Radio Detection And Ranging) applications and consists of one low-loss RF (Radio Frequency) layer and several FR4 layers. In line with previous work [1], the mechanical material properties of the low-loss RF laminate material are found to be the key factor. Simulation is used to systematically screen for mechanical properties which are favorable for achieving a high solder joint reliability on the unconstrained PCBs used for standardized solder joint reliability testing. A simplified virtual assessment of PCBs constrained by the mounting in system module housings is done. Both simulation and experimental results show that RF laminate materials with low Young’s modulus are the class of materials which allows for the highest solder joint reliability for all the conditions investigated in this study.

Effects of Void, Crack, and PCB Thickness on the Solder Joint Reliability of Wafer-Level Chip-Scale Package (WLCSP) Assemblies

2002 ◽  
Author(s):  
John Lau ◽  
Yida Zou ◽  
Sergio Camerlo
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Temperature Cycling ◽  
Circuit Board ◽  
J Integral ◽  
Wafer Level ◽  
Solder Joint Reliability ◽  
Printed Circuit ◽  
Joint Reliability ◽  
Chip Scale Package

The creep analyses of solder-bumped wafer-level chip-scale package (WLCSP) on printed circuit board (PCB) subjected to temperature cycling loading are presented. Emphasis is placed on the effects of PCB thickness on the solder joint reliability of the WLCSP assembly. Also, the effects of crack-length on the crack tip characteristics such as the J-integral in the WLCSP solder joint are studied by the fracture mechanics method. Finally, the effects of voids on the crack growth in the WLCSP solder joint are investigated.

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