An efficient test relaxation technique for synchronous sequential circuits

Proceedings. 21st VLSI Test Symposium, 2003. ◽

10.1109/vtest.2003.1197649 ◽

2003 ◽

Cited By ~ 5

Author(s):

A. El-Maleh ◽

K. Al-Utaibi

Keyword(s):

Sequential Circuits ◽

Relaxation Technique ◽

Efficient Test ◽

Synchronous Sequential Circuits

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An Efficient Test Relaxation Technique for Synchronous Sequential Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2004.828110 ◽

2004 ◽

Vol 23 (6) ◽

pp. 933-940 ◽

Cited By ~ 21

Author(s):

A. El-Maleh ◽

K. Al-Utaibi

Keyword(s):

Sequential Circuits ◽

Relaxation Technique ◽

Efficient Test ◽

Synchronous Sequential Circuits

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An efficient test relaxation technique for combinational & full-scan sequential circuits

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) ◽

10.1109/vts.2002.1011111 ◽

2003 ◽

Cited By ~ 34

Author(s):

A. El-Maleh ◽

A. Al-Suwaiyan

Keyword(s):

Sequential Circuits ◽

Relaxation Technique ◽

Efficient Test ◽

Full Scan

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New methods for parallel pattern fast fault simulation for synchronous sequential circuits

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246617 ◽

2002 ◽

Author(s):

M. Mojtahedi ◽

W. Geisselhardt

Keyword(s):

Fault Simulation ◽

Sequential Circuits ◽

New Methods ◽

Synchronous Sequential Circuits ◽

Parallel Pattern

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Dynamic test compaction for synchronous sequential circuits using static compaction techniques

Proceedings of Annual Symposium on Fault Tolerant Computing ◽

10.1109/ftcs.1996.534594 ◽

2002 ◽

Cited By ~ 21

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Dynamic Test ◽

Sequential Circuits ◽

Test Compaction ◽

Synchronous Sequential Circuits ◽

Static Compaction

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Resynthesis and retiming of synchronous sequential circuits

1993 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.1993.394063 ◽

2002 ◽

Cited By ~ 4

Author(s):

S. Lejmi ◽

B. Kaminska ◽

E. Wagneur

Keyword(s):

Sequential Circuits ◽

Synchronous Sequential Circuits

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Built-in test sequence generation for synchronous sequential circuits based on loading and expansion of test subsequences

Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99 ◽

10.1145/309847.310052 ◽

1999 ◽

Author(s):

Irith Pomeranz ◽

Sudhakar M. Reddy

Keyword(s):

Sequential Circuits ◽

Test Sequence ◽

Sequence Generation ◽

Synchronous Sequential Circuits ◽

Test Sequence Generation

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Synchronous Sequential Circuits

Computer Organization, Design, and Architecture, Fifth Edition ◽

10.1201/b16435-5 ◽

2013 ◽

pp. 139-204

Keyword(s):

Sequential Circuits ◽

Synchronous Sequential Circuits

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Synchronous Sequential Circuits

Introduction to Logic Design ◽

10.1201/9781482289848-6 ◽

2018 ◽

pp. 243-319

Author(s):

Sajjan G. Shiva

Keyword(s):

Sequential Circuits ◽

Synchronous Sequential Circuits

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Analysis of multiple faults in synchronous sequential circuits by Boolean difference techniques

10.2172/6793029 ◽

1978 ◽

Author(s):

L.H. Goldstein

Keyword(s):

Sequential Circuits ◽

Multiple Faults ◽

Synchronous Sequential Circuits

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Test generation for synchronous sequential circuits to reduce storage requirements

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259) ◽

10.1109/ats.1998.741655 ◽

2002 ◽

Cited By ~ 1

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Generation ◽

Sequential Circuits ◽

Synchronous Sequential Circuits

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