On Testing of Superscalar Processors in Functional Mode for Delay Faults

2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID) ◽

10.1109/vlsid.2017.58 ◽

2017 ◽

Cited By ~ 3

Author(s):

Nihar Hage ◽

Rohini Gulve ◽

Masahiro Fujita ◽

Virendra Singh

Keyword(s):

Superscalar Processors ◽

Delay Faults ◽

Functional Mode

Download Full-text

Testing superscalar processors in functional mode

International Conference on Field Programmable Logic and Applications, 2005. ◽

10.1109/fpl.2005.1515837 ◽

2005 ◽

Cited By ~ 1

Author(s):

V. Singh ◽

M. Inoue ◽

K.K. Saluja ◽

H. Fujiwara

Keyword(s):

Superscalar Processors ◽

Functional Mode

Download Full-text

High-bandwidth data memory systems for superscalar processors

ACM SIGARCH Computer Architecture News ◽

10.1145/106975.106980 ◽

1991 ◽

Vol 19 (2) ◽

pp. 53-62 ◽

Cited By ~ 1

Author(s):

Gurindar S. Sohi ◽

Manoj Franklin

Keyword(s):

Memory Systems ◽

Superscalar Processors ◽

Data Memory ◽

High Bandwidth

Download Full-text

High-bandwidth data memory systems for superscalar processors

ACM SIGPLAN Notices ◽

10.1145/106973.106980 ◽

1991 ◽

Vol 26 (4) ◽

pp. 53-62 ◽

Cited By ~ 3

Author(s):

Gurindar S. Sohi ◽

Manoj Franklin

Keyword(s):

Memory Systems ◽

Superscalar Processors ◽

Data Memory ◽

High Bandwidth

Download Full-text

On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults

22nd International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2012.6339167 ◽

2012 ◽

Cited By ~ 8

Author(s):

Petr Pfeifer ◽

Zdenek Pliva

Keyword(s):

Delay Faults ◽

Fpga Design

Download Full-text

Parallel pattern fault simulation of path delay faults

Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference - DAC '89 ◽

10.1145/74382.74442 ◽

1989 ◽

Cited By ~ 46

Author(s):

M. Schulz ◽

F. Fink ◽

K. Fuchs

Keyword(s):

Fault Simulation ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults ◽

Parallel Pattern

Download Full-text

A satisfiability-based test generator for path delay faults in combinational circuits

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545574 ◽

2005 ◽

Cited By ~ 30

Author(s):

Chih-Ang Chen ◽

S.K. Gupta

Keyword(s):

Delay Faults ◽

Path Delay ◽

Combinational Circuits ◽

Path Delay Faults

Download Full-text

Fast test pattern generation for all path delay faults considering various test classes

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246529 ◽

2002 ◽

Cited By ~ 15

Author(s):

K. Fuchs ◽

H.C. Wittmann ◽

K.J. Antreich

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults

Download Full-text

Code scheduling for VLIW/superscalar processors with limited register files

ACM SIGMICRO Newsletter ◽

10.1145/144965.145802 ◽

1992 ◽

Vol 23 (1-2) ◽

pp. 197-201

Author(s):

Tokuzo Kiyohara ◽

John C. Gyllenhaal

Keyword(s):

Superscalar Processors ◽

Code Scheduling

Download Full-text

Functional-based ATPG for path delay faults

2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390) ◽

10.1109/ssmsd.2000.836465 ◽

2002 ◽

Cited By ~ 1

Author(s):

M. Michael ◽

S. Tragoudas

Keyword(s):

Delay Faults ◽

Path Delay ◽

Path Delay Faults

Download Full-text

Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors

Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000 ◽

10.1109/micro.2000.898083 ◽

2002 ◽

Cited By ~ 14

Author(s):

A. Baniasadi ◽

A. Moshovos

Keyword(s):

Superscalar Processors

Download Full-text