A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems ◽

10.1109/vlsid.2014.11 ◽

2014 ◽

Cited By ~ 3

Author(s):

Spencer K. Millican ◽

Kewal K. Saluja

Keyword(s):

Integrated Circuits ◽

3D Integrated Circuits ◽

Partitioning Technique

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A Security-Aware Pre-partitioning Technique for 3D Integrated Circuits

2017 18th International Workshop on Microprocessor and SOC Test and Verification (MTV) ◽

10.1109/mtv.2017.20 ◽

2017 ◽

Cited By ~ 4

Author(s):

Siroos Madani ◽

Magdy Bayoumi

Keyword(s):

Integrated Circuits ◽

3D Integrated Circuits ◽

Partitioning Technique

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Experimental investigation of electromigration failure in Cu–Sn–Cu micropads in 3D integrated circuits

Microelectronic Engineering ◽

10.1016/j.mee.2014.03.003 ◽

2014 ◽

Vol 122 ◽

pp. 46-51 ◽

Cited By ~ 13

Author(s):

Zhihong Huang ◽

Robert E. Jones ◽

Ankur Jain

Keyword(s):

Experimental Investigation ◽

Integrated Circuits ◽

3D Integrated Circuits

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Analysis of critical thermal issues in 3D integrated circuits

International Journal of Heat and Mass Transfer ◽

10.1016/j.ijheatmasstransfer.2016.02.010 ◽

2016 ◽

Vol 97 ◽

pp. 337-352 ◽

Cited By ~ 18

Author(s):

Fatemeh Tavakkoli ◽

Siavash Ebrahimi ◽

Shujuan Wang ◽

Kambiz Vafai

Keyword(s):

Integrated Circuits ◽

3D Integrated Circuits

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3D Integrated Circuits Layout Optimization Game

Artificial Intelligence and Soft Computing - Lecture Notes in Computer Science ◽

10.1007/978-3-319-59060-8_40 ◽

2017 ◽

pp. 444-453

Author(s):

Katarzyna Grzesiak-Kopeć ◽

Leszek Nowak ◽

Maciej Ogorzałek

Keyword(s):

Integrated Circuits ◽

Layout Optimization ◽

3D Integrated Circuits

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Exploration of the Thermal Design Space in 3D Integrated Circuits

Physical Design for 3D Integrated Circuits ◽

10.1201/b19225-11 ◽

2017 ◽

pp. 245-259

Author(s):

Sumeet S. Kumar ◽

Amir Zjajo ◽

Rene van Leuken

Keyword(s):

Integrated Circuits ◽

Design Space ◽

Thermal Design ◽

3D Integrated Circuits

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Electromigration Alleviation Techniques for 3D Integrated Circuits

High Performance Computing for Big Data ◽

10.1201/9781315155524-4 ◽

2017 ◽

pp. 37-58

Author(s):

Yuanqing Cheng ◽

Aida Todri-Sanial ◽

Alberto Bosio ◽

Luigi Dilillo ◽

Patrick Girard ◽

...

Keyword(s):

Integrated Circuits ◽

3D Integrated Circuits

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The fabrication of poly-Si MOSFETs using ultra-thin high-K/metal-gate stack for monolithic 3D integrated circuits technology applications

2011 International Semiconductor Device Research Symposium (ISDRS) ◽

10.1109/isdrs.2011.6135219 ◽

2011 ◽

Author(s):

T.-H. Wu ◽

M. H. Lee

Keyword(s):

Integrated Circuits ◽

Metal Gate ◽

Gate Stack ◽

High K ◽

Technology Applications ◽

3D Integrated Circuits

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Proposed static timing analysis framework for extracted 3D integrated circuits (3D-STA)

2015 International 3D Systems Integration Conference (3DIC) ◽

10.1109/3dic.2015.7334604 ◽

2015 ◽

Author(s):

Mohamed N. ElBahey ◽

DiaaEldin S. Khalil ◽

Hani F. Ragai

Keyword(s):

Integrated Circuits ◽

Timing Analysis ◽

Analysis Framework ◽

Static Timing Analysis ◽

Static Timing ◽

3D Integrated Circuits

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Arbitrary Modeling of TSVs for 3D Integrated Circuits

10.1007/978-3-319-07611-9 ◽

2015 ◽

Cited By ~ 1

Author(s):

Khaled Salah ◽

Yehea Ismail ◽

Alaa El-Rouby

Keyword(s):

Integrated Circuits ◽

3D Integrated Circuits

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RF Properties of Carbon Nanotube / Copper Composite Through Silicon Via Based CPW Structure for 3D Integrated Circuits

2019 IEEE 14th Nanotechnology Materials and Devices Conference (NMDC) ◽

10.1109/nmdc47361.2019.9084012 ◽

2019 ◽

Author(s):

Andreas Nylander ◽

Marlene Bonmann ◽

Andrei Vorobiev ◽

Josef Hansson ◽

Nan Wang ◽

...

Keyword(s):

Carbon Nanotube ◽

Integrated Circuits ◽

Through Silicon Via ◽

3D Integrated Circuits ◽

Copper Composite

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