Self-Immunity Technique to Improve Register File Integrity Against Soft Errors

2011 ◽  
Author(s):  
H Amrouch ◽  
J Henkel
Keyword(s):  
Soft Errors ◽  
Register File

scholarly journals Characterizing System-Level Masking Effects against Soft Errors

Electronics ◽  
2021 ◽  
Vol 10 (18) ◽  
pp. 2286
Author(s):  
Yohan Ko
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
System Reliability ◽  
Soft Errors ◽  
System Level ◽  
Register File ◽  
System Failures ◽  
Early Design ◽  
Lifetime Analysis ◽  
Estimate Reliability

From early design phases to final release, the reliability of modern embedded systems against soft errors should be carefully considered. Several schemes have been proposed to protect embedded systems against soft errors, but they are neither always functional nor robust, even with expensive overhead in terms of hardware area, performance, and power consumption. Thus, system designers need to estimate reliability quantitatively to apply appropriate protection techniques for resource-constrained embedded systems. Vulnerability modeling based on lifetime analysis is one of the most efficient ways to quantify system reliability against soft errors. However, lifetime analysis can be inaccurate, mainly because it fails to comprehensively capture several system-level masking effects. This study analyzes and characterizes microarchitecture-level and software-level masking effects by developing an automated framework with exhaustive fault injections (i.e., soft errors) based on a cycle-accurate gem5 simulator. We injected faults into a register file because errors in the register file can easily be propagated to other components in a processor. We found that only 5% of injected faults can cause system failures on an average over benchmarks, mainly from the MiBench suite. Further analyses showed that 71% of soft errors are overwritten by write operations before being used, and the CPU does not use 20% of soft errors at all after fault injections. The remainder are also masked by several software-level masking effects, such as dynamically dead instructions, compare and logical instructions that do not change the result, and incorrect control flows that do not affect program outputs.

Analysis of Induced End-of-Life Failures in SRAM Through Nanoprobing

2018 ◽  
Author(s):  
Oberon Dixon-Luinenburg ◽  
Jordan Fine
Keyword(s):  
End Of Life ◽  
Soft Errors ◽  
Cause Analysis ◽  
New Approach ◽  
Performance Loss ◽  
Root Cause ◽  
Long Period ◽  
Atomic Force ◽  
Stress Resultant ◽  
Voltage Stress

Abstract In this paper, we demonstrate a novel nanoprobing approach to establish cause-and-effect relationships between voltage stress and end-of-life performance loss and failure in SRAM cells. A Hyperion II Atomic Force nanoProber was used to examine degradation for five 6T cells on an Intel 14 nm processor. Ten minutes of asymmetrically applied stress at VDD=2 V was used to simulate a ‘0’ bit state held for a long period, subjecting each pullup and pulldown to either VDS or VGS stress. Resultant degradation caused read and hold margins to be reduced by 20% and 5% respectively for the ‘1’ state and 5% and 2% respectively for the ‘0’ state. ION was also reduced, for pulldown and pullup respectively, by 4.5% and 5.4% following VGS stress and 2.6% and 33.8% following VDS stress. Negative read margin failures, soft errors, and read time failures all become more prevalent with these aging symptoms whereas write stability is improved. This new approach enables highly specific root cause analysis and failure prediction for end-of-life in functional on-product SRAM.

Instruction Scheduling Algorithm for Register File Connectivity Clustered VLIW Architecture

2009 ◽  
Vol 31 (1) ◽  
pp. 127-132
Author(s):  
Zhi-Xiong ZHOU ◽  
Hu HE ◽  
Xu YANG ◽  
Yan-Jun ZHANG ◽  
Yi-He SUN
Keyword(s):  
Scheduling Algorithm ◽  
Instruction Scheduling ◽  
Register File

Active-Cycle Based Register File Design for Reduced Ports and Energy

2009 ◽  
Vol 31 (2) ◽  
pp. 299-308 ◽  
Author(s):  
Yu-Lai ZHAO ◽  
Xian-Feng LI ◽  
Dong TONG ◽  
Han-Xin SUN ◽  
Jie CHEN ◽  
...  
Keyword(s):  
Register File ◽  
File Design

Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs

2021 ◽  
Author(s):  
Alexandra Zimpeck ◽  
Cristina Meinhardt ◽  
Laurent Artola ◽  
Ricardo Reis
Keyword(s):  
Soft Errors ◽  
Process Variability
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