Analog macromodeling for combined resistive vias, resistive bridges, and capacitive crosstalk delay faults

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06) ◽

10.1109/vlsid.2006.47 ◽

2006 ◽

Cited By ~ 4

Author(s):

S. Chary ◽

M.L. Bushnell

Keyword(s):

Delay Faults ◽

Resistive Bridges

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Automatic path-delay fault test generation for combined resistive vias, resistive bridges, and capacitive crosstalk delay faults

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06) ◽

10.1109/vlsid.2006.51 ◽

2006 ◽

Cited By ~ 2

Author(s):

S. Chary ◽

M.L. Bushnell

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault ◽

Resistive Bridges

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Diagnosis of delay faults due to resistive bridges, delay variations and defects

2006 15th Asian Test Symposium ◽

10.1109/ats.2006.261023 ◽

2006 ◽

Cited By ~ 2

Author(s):

Lei Wang ◽

Sandeep Gupta ◽

Melvin Breuer

Keyword(s):

Delay Faults ◽

Delay Variations ◽

Resistive Bridges

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On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults

22nd International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2012.6339167 ◽

2012 ◽

Cited By ~ 8

Author(s):

Petr Pfeifer ◽

Zdenek Pliva

Keyword(s):

Delay Faults ◽

Fpga Design

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Parallel pattern fault simulation of path delay faults

Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference - DAC '89 ◽

10.1145/74382.74442 ◽

1989 ◽

Cited By ~ 46

Author(s):

M. Schulz ◽

F. Fink ◽

K. Fuchs

Keyword(s):

Fault Simulation ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults ◽

Parallel Pattern

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A satisfiability-based test generator for path delay faults in combinational circuits

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545574 ◽

2005 ◽

Cited By ~ 30

Author(s):

Chih-Ang Chen ◽

S.K. Gupta

Keyword(s):

Delay Faults ◽

Path Delay ◽

Combinational Circuits ◽

Path Delay Faults

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Fast test pattern generation for all path delay faults considering various test classes

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246529 ◽

2002 ◽

Cited By ~ 15

Author(s):

K. Fuchs ◽

H.C. Wittmann ◽

K.J. Antreich

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults

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Functional-based ATPG for path delay faults

2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390) ◽

10.1109/ssmsd.2000.836465 ◽

2002 ◽

Cited By ~ 1

Author(s):

M. Michael ◽

S. Tragoudas

Keyword(s):

Delay Faults ◽

Path Delay ◽

Path Delay Faults

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An Automatic Test Generation Method for Crosstalk Delay Faults Using Modified FAN Algorithm

Test Generation of Crosstalk Delay Faults in VLSI Circuits ◽

10.1007/978-981-13-2493-2_4 ◽

2018 ◽

pp. 57-77

Author(s):

S. Jayanthy ◽

M. C. Bhuvaneswari

Keyword(s):

Test Generation ◽

Delay Faults ◽

Automatic Test Generation ◽

Automatic Test ◽

Fan Algorithm

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On-line detection of environmentally-induced delay faults in CMOS wave pipelined circuits

Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1996.551963 ◽

2002 ◽

Cited By ~ 2

Author(s):

A. Martinez-Smith ◽

R. Sridhar

Keyword(s):

Line Detection ◽

Delay Faults ◽

On Line ◽

Pipelined Circuits

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Exploring Linear Structures of Critical Path Delay Faults to Reduce Test Efforts

2006 IEEE/ACM International Conference on Computer Aided Design ◽

10.1109/iccad.2006.320072 ◽

2006 ◽

Author(s):

Shun-yen Lu ◽

Pei-ying Hsieh ◽

Jing-jia Liou

Keyword(s):

Critical Path ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults ◽

Linear Structures ◽

Critical Path Delay

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