A practical power model of AMBA system for high-level power analysis

A new approach for power analysis of microprocessors has recently been proposed [14]. The idea is to look at the power consumption in a microprocessor from the point of view of the actual software executing on the processor. The basic component of this approach is a measurement based, instruction-level power analysis technique. The technique allows for the development of an instruction-level power model for the given processor, which can be used to evaluate software in terms of the power consumption, and for exploring the optimization of software for lower power. This paper describes the application of this technique for a comprehensive instruction-level power analysis of a commercial 32-bit RISC-based embedded microcontroller. The salient results of the analysis and the basic instruction-level power model are described. Interesting observations and insights based on the results are also presented. Such an instruction-level power analysis can provide cues as to what optimizations in the micro-architecture design of the processor would lead to the most effective power savings in actual software applications. Wherever the results indicate such optimizations, they have been discussed. Furthermore, ideas for low power software design, as suggested by the results, are described in this paper as well.

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Investigation Role of Sbox to Leakage DPA Information for TDES in FPGA Targets

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.256-259.2820 ◽

2012 ◽

Vol 256-259 ◽

pp. 2820-2825

Author(s):

A Zadali Mohammad Kootiani ◽

P Abedi

Keyword(s):

Power Analysis ◽

Hardware Implementation ◽

Digital Simulation ◽

Power Model ◽

Great Effort ◽

Differential Power Analysis ◽

Encryption Algorithms

Differential power analysis (DPA) attack is an important threat that researchers spend great effort to make crypto algorithms resistant against DPA attacks. In order to determine whether the hardware has DPA leakage before manufacturing, an accurate power model in digital simulation has been generated. FPGAs Arrays are attractive options for hardware implementation of encryption algorithms. In this paper, we show generated power model by using integer numbers whole DES’s rounds vs. S-Box alone, and this method gives more realistic results to determine the effectiveness of the improvements protect whole DES rather than in which only informer elements in the DES round. In particular this allows the user to isolate some parts of its implementation in order to analyze information leakages directly linked to them. We review s-box because it’s get 2kbit or 20% CLB slice from FPGA to implement DES or TDES. This paper try to identify role of Sbox in DPA.

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