An integrated circuit with transmit beamforming flip-chip bonded to a 2-D CMUT array for 3-D ultrasound imaging

2009 ◽  
Vol 56 (10) ◽  
pp. 2145-2156 ◽  
Author(s):  
I. O. Wygant ◽  
N. S. Jamal ◽  
H. J. Lee ◽  
A. Nikoozadeh ◽  
O. Oralkan ◽  
...  
Keyword(s):  
Ultrasound Imaging ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Transmit Beamforming

scholarly journals Fabrication and Packaging of CMUT Using Low Temperature Co-Fired Ceramic

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 553 ◽  
Author(s):  
Fikret Yildiz ◽  
Tadao Matsunaga ◽  
Yoichi Haga
Keyword(s):  
Low Temperature ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Ultrasonic Transducer ◽  
Silicon On Insulator ◽  
Anodic Bonding ◽  
Lateral Side ◽  
Membrane Thickness ◽  
Bonding Performance ◽  
Complex Admittance

This paper presents fabrication and packaging of a capacitive micromachined ultrasonic transducer (CMUT) using anodically bondable low temperature co-fired ceramic (LTCC). Anodic bonding of LTCC with Au vias-silicon on insulator (SOI) has been used to fabricate CMUTs with different membrane radii, 24 µm, 25 µm, 36 µm, 40 µm and 60 µm. Bottom electrodes were directly patterned on remained vias after wet etching of LTCC vias. CMUT cavities and Au bumps were micromachined on the Si part of the SOI wafer. This high conductive Si was also used as top electrode. Electrical connections between the top and bottom of the CMUT were achieved by Au-Au bonding of wet etched LTCC vias and bumps during anodic bonding. Three key parameters, infrared images, complex admittance plots, and static membrane displacement, were used to evaluate bonding success. CMUTs with a membrane thickness of 2.6 µm were fabricated for experimental analyses. A novel CMUT-IC packaging process has been described following the fabrication process. This process enables indirect packaging of the CMUT and integrated circuit (IC) using a lateral side via of LTCC. Lateral side vias were obtained by micromachining of fabricated CMUTs and used to drive CMUTs elements. Connection electrodes are patterned on LTCC side via and a catheter was assembled at the backside of the CMUT. The IC was mounted on the bonding pad on the catheter by a flip-chip bonding process. Bonding performance was evaluated by measurement of bond resistance between pads on the IC and catheter. This study demonstrates that the LTCC and LTCC side vias scheme can be a potential approach for high density CMUT array fabrication and indirect integration of CMUT-IC for miniature size packaging, which eliminates problems related with direct integration.

“Cleaning”- The Dirty Word in Packaging Assembly

2010 ◽  
Vol 2010 (1) ◽  
pp. 000742-000746
Author(s):  
Rich Brooks
Keyword(s):  
Thermal Energy ◽  
Integrated Circuit ◽  
Flip Chip ◽  
New Technologies ◽  
Cleaning Process ◽  
Maximum Performance ◽  
Low Profile ◽  
Total Process ◽  
Temperature And Pressure

A majority of the package assembly facilities are using only DI water to remove flux residue from under flip-chip devices, prior to an underfill process. As the new technologies are being implemented, not only has DI water reached its limitations, but some cleaning chemistries are not able to perform adequately to remove ALL of the flux residues. Complete cleaning and removal of the flux residues under low profile components are critical to maintain the reliability of the integrated circuit. Therefore, the cleaning process must be carefully examined and optimized to obtain maximum performance for removing the flux residues. The total cleaning process can be broken down into two subsets:Static Cleaning rate & Dynamic Cleaning rate The Static Cleaning rate is ability of the cleaning chemistry to remove or dissolve the residue in the absence of temperature and pressure. The Dynamic Cleaning rate involves the kinetic forces and energy to remove the residue. This includes the Thermal energy and Impingement energy required to remove the flux residue. The sum of these two cleaning rates (Static and Dynamic cleaning rates) equal the Total Process Cleaning rate (see formula below). This paper will review cleaning problems brought about with the implementation of the latest technologies and explain how the cleaning process can be optimized to guarantee the reliability of the assemblies.

Experiment and Numerical Analysis of the Residual Stresses in Underfill Resins for Flip Chip Package Applications

2005 ◽  
Vol 127 (1) ◽  
pp. 47-51 ◽  
Author(s):  
Man-Lung Sham ◽  
Jang-Kyo Kim
Keyword(s):  
Numerical Analysis ◽  
Residual Stresses ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Flexural Modulus ◽  
Curing Temperature ◽  
Electronic Packages ◽  
Element Analysis ◽  
Plastic Package

Polymeric encapsulant is widely used to protect the integrated circuit chips and thus to enhance the reliability of electronic packages. Residual stresses are introduced in the plastic package when the polymer is cooled from the curing temperature to ambient, from which many reliability issues arise, including warpage of the package, premature interfacial failure, and degraded interconnections. Bimaterial strip bending experiment has been employed successfully to monitor the evolution of the residual stresses in underfrill resins for flip chip applications. A numerical analysis is developed to predict the residual stresses, which agree well with the experimental measurements. The changes of material properties, such as flexural modulus and coefficient of thermal expansion, of the resins with temperature are taken into account in the finite element analysis.

On the Multiscale Finite Element Analysis for Interfacial Fracture in Cu/Low-K Interconnects

2007 ◽  
Author(s):  
Tz-Cheng Chiu ◽  
Huang-Chun Lin
Keyword(s):  
Thin Film ◽  
Fracture Mechanics ◽  
Interface Crack ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Thermal Loading ◽  
Global Analysis ◽  
Crack Problem ◽  
Element Analysis ◽  
Low K

The interface crack problem in integrated circuit devices was considered by using global and local modeling approach. In the global analysis the thin film interconnect was modeled by a homogenized layer with material constants obtained from representative volume element (RVE) analysis. Local analyses were then considered to determine fracture mechanics parameters. It was shown that the multiscale model with RVE approach gives accurate fracture mechanics parameters for an interface crack under either thermal or mechanical loads; while significant error was observed when the thin film layers are ignored in the global analysis. The problem of an interface crack between low-k dielectric and etch-stop thin film in a flip-chip package under thermal loading was also investigated as an application example of the multiscale modeling.

Flip Chip Underfill RF Characterization

2019 ◽  
Vol 2019 (1) ◽  
pp. 000243-000247
Author(s):  
Robert B. Paul ◽  
A. Ege Engin ◽  
Jerry Aguirre
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Speed ◽  
Flip Chip ◽  
Power Integrity ◽  
Cavity Resonators ◽  
Dielectric Characterization ◽  
Noise Coupling ◽  
Solder Bumps ◽  
Underfill Material

Abstract To develop reliable high-speed packages, characterization of the underfill material used in the flip-chip process has become of greater importance. The underfill, typically an epoxy resin-based material, offers thermal and structural benefits for the integrated circuit (IC) on package. With so many inputs and outputs (IOs) in close proximity to one another, the integrated circuits on package can have unexpected signal and power integrity issues. Furthermore, chip packages can support signals only up to the frequency where noise coupling (e.g., crosstalk, switching noise, etc.) leads to the malfunctioning of the system. Vertical interconnects, such as vias and solder bumps, are major sources of noise coupling. Inserting ground references between every signal net is not practical. For the solder bumps, the noise coupling depends on the permittivity of the underfill material. Therefore, characterizing the permittivity of the underfill material helps in predicting signal and power integrity issues. Such liquid or semi-viscous materials are commonly characterized from a simple fringe capacitance model of an open-ended coaxial probe immersed in the material. The open-ended coaxial method, however, is not as accurate as resonator-based methods. There is a need for a methodology to accurately extract the permittivity of liquid or semi-viscous materials at high frequencies. The proposed method uses solid walled cavity resonators, where the resonator is filled with the underfill material and cured. Dielectric characterization is a complex process, where the physical characteristics of the cavities must be known or accurately measured. This includes the conductivity of the conductors, roughness of the conductors, the dimensions of the cavity, and the port pin locations. This paper discusses some of the challenges that are encountered when characterizing dielectrics with cavity resonators. This characterization methodology can also be used to characterize other materials of interest.

A Hybrid Antenna in Package Solution Using FOWLP Technology

2021 ◽  
Author(s):  
XueSong Zhang ◽  
Qian Wang ◽  
Bo Wang ◽  
Gang Wang ◽  
Xin Gu ◽  
...  
Keyword(s):  
Millimeter Wave ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Transmission Loss ◽  
Rapid Development ◽  
Coplanar Waveguide ◽  
Organic Substrate ◽  
Hybrid Integration ◽  
Wafer Level ◽  
Monolithic Integrated Circuit

Abstract Widespread millimeter wave applications have promoted rapid development of System in Package (SiP) and Antenna in Package (AiP). Most AiP structures take the form of flip chip on antenna substrate, where interconnect losses are caused by solder bumps, and manufacturing difficulties may be encountered for chips with fine pad pitches. Fan-out wafer level package (FOWLP) with antenna patterning on Redistributed Layers (RDL) is another method for mm-wave AiP realization. In this project a hybrid integration AiP structure is developed. The Microwave Monolithic Integrated Circuit (MMIC) chip and antenna unit are integrated with chip-first FOWLP process. By using multilayer organic substrate and fine pitch RDL interconnection, proper antenna performance and lower transmission loss can be achieved. Modified coplanar waveguide is adopted to feed 2x2 aperture array formed on RDL. Package warpage is evaluated using ANSYS and Shadow Moire measurement. The antenna realizes bandwidth 25% and gain 8.5dBi using aperture-coupled stacked patch for 60GHz digital communication system. The proposed approach is a convenient solution for the hybrid integration of millimeter wave AiP systems.

Sign in / Sign up

Export Citation Format

Share Document