Operational Amplifier Based Test Structure for Quantifying Transistor Threshold Voltage Variation

2009 ◽  
Vol 22 (1) ◽  
pp. 51-58 ◽  
Author(s):  
Brian L. Ji ◽  
Dale J. Pearson ◽  
Isaac Lauer ◽  
Franco Stellari ◽  
David J. Frank ◽  
...  
2019 ◽  
Vol 14 (1) ◽  
pp. 1-6
Author(s):  
Alberto Vinícius Oliveira ◽  
Guilherme Vieira Gonçalves ◽  
Paula Ghedini Der Agopian ◽  
João Antonio Martino ◽  
Jérôme Mitard ◽  
...  

The implementation of a barrier potential layer underneath the channel region, well known as Ground Plane (GP) implantation, and its influence on the performance of relaxed germanium pFinFET devices is investigated in this manuscript. This study aims to explain the fin width dependence of the threshold voltage from experimental data and evaluates the ground plane doping concentration and its depth influence on relaxed p-type channel germanium FinFET parameters, as threshold voltage, transconductance and subthreshold swing, through Technology Computer-Aided Design (TCAD) numerical simulations. The threshold voltage variation reaches up to 80 mV from the narrowest device to the widest one, considering the studied range of ground plane doping concentration. Concerning the subthreshold swing parameter, neither the GP doping concentration, nor its depth play a significant role since the electrostatic coupling is predominant.


2018 ◽  
Vol 201 ◽  
pp. 02002
Author(s):  
Hao-Ping Chan ◽  
Yu-Cherng Hung

By using 0.35-um CMOS process, this work achieves a design of analogous band-gap reference voltage circuit with low temperature coefficient. The proposed circuit operates at 3V and generates a reference current of 44 uA. The HSPICE simulation results show the temperature coefficient of this circuit is 23 ppm/°C at range of -10 °C to 100 °C, and the line regulation (the ratio of output current variation to supply voltage variation) is estimated as 1.95 uA/V from supply voltage variation of 3 V to 5 V. The experimental chip is fabricated and measured. The circuit provides adjustable capability for output voltage among temperature variation of -10 - 100 °C. The chip area is 534 × 695 um2. In this new design, the operational amplifier is not necessary. The chip design effort can be great reduced.


2020 ◽  
Vol 41 (3) ◽  
pp. 373-376
Author(s):  
Sanghyun Ban ◽  
Hyejung Choi ◽  
Wootae Lee ◽  
Seokman Hong ◽  
Hwanjun Zang ◽  
...  

2001 ◽  
Vol 48 (9) ◽  
pp. 1995-2001 ◽  
Author(s):  
K. Takeuchi ◽  
R. Koh ◽  
T. Mogami

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