Material removal regions in chemical mechanical planarization for submicron integrated circuit fabrication: coupling effects of slurry chemicals, abrasive size distribution,and wafer-pad contact area

2003 ◽  
Vol 16 (1) ◽  
pp. 45-56 ◽  
Author(s):  
Jianfeng Luo ◽  
D.A. Dornfeld
Keyword(s):  
Size Distribution ◽  
Contact Area ◽  
Integrated Circuit ◽  
Material Removal ◽  
Chemical Mechanical Planarization ◽  
Coupling Effects ◽  
Integrated Circuit Fabrication ◽  
Circuit Fabrication ◽  
Abrasive Size

A Study to Estimate the Number of Active Particles in CMP

2009 ◽  
Vol 1157 ◽  
Author(s):  
Jeremiah Mpagazehe ◽  
Geo Thukalil ◽  
C. Fred Higgs
Keyword(s):  
Integrated Circuit ◽  
Material Removal ◽  
Removal Rate ◽  
Analytical Models ◽  
Wear Process ◽  
Active Particles ◽  
Integrated Circuit Fabrication ◽  
Circuit Fabrication ◽  
Analytical Approaches ◽  
Cmp Model

AbstractTo improve yield rates during integrated circuit fabrication a better understanding of the material removal process during CMP is sought. Many material removal models have been generated to predict the material removal rate (MRR) during CMP. The majority of such models estimate that the MRR is equal to the material removed by a single particle multiplied by the total number of particles contributing to the wear process. Particles contributing to the wear process are known as ‘active particles’. Several authors have proposed analytical models to estimate this quantity. This work introduces a new method for estimating the number of active particles in CMP by deducing it from the polish results of a multi-physics CMP model. By employing the particle-augmented mixed lubrication model (PAML) developed by Terrell and Higgs (2008), it is possible to determine the number of active particles in CMP. The predictions of PAML are compared with two popular analytical approaches which have been commonly used to predict the number of active particles during CMP.

Evolution of Stress During Formation of Titanium Disilicide by Rta and Tube Furnace Annealing

1990 ◽  
Vol 202 ◽  
Author(s):  
J.F. Jongste ◽  
O.B. Loopstra ◽  
G.C.A.M. Janssen ◽  
S. Radelaar
Keyword(s):  
Integrated Circuit ◽  
Thermal Processing ◽  
Reaction Rates ◽  
Titanium Disilicide ◽  
Furnace Annealing ◽  
Integrated Circuit Fabrication ◽  
Annealing Step ◽  
Circuit Fabrication ◽  
The Difference ◽  
Processing Steps

Integrated circuit fabrication consists of many processing steps: e.g. lithography, etching, implantation and metallization. Some of these processes are combined with thermal processing. Heat treatments require special attention because previous fabrication steps may be influenced: e.g. dopant profiles may be deteriorated. The amount of interference of an annealing step with a former process is determined by the ratio of the reaction rates (and hence by the difference in activation energies).

A Fresh Insight into Film Morphology Measurement Techniques for Advanced Ulsi Manufacturing

1993 ◽  
Vol 309 ◽  
Author(s):  
Seshadri Ramaswami
Keyword(s):  
Grain Size ◽  
Integrated Circuit ◽  
Measurement Techniques ◽  
Film Morphology ◽  
Integrated Circuit Fabrication ◽  
Circuit Fabrication ◽  
Non Destructive ◽  
Fresh Insight ◽  
Insight Into

AbstractA laser based non-destructive technique has been used to study the morphology of sputterdeposited aluminum alloy films. The data emanating from the Therma-wave Imager that makes use of this principle, has been correlated with reflectivity, grain size and micro-roughness of the film. In addition, through the use of a case study, this paper demonstrates the utility of this application as an in-line monitor in an integrated circuit fabrication line.

Silicon Rapid Thermal Processing with Ripple Pyrometry

1997 ◽  
Vol 502 ◽  
Author(s):  
A. T. Fiory
Keyword(s):  
Integrated Circuit ◽  
Thermal Processing ◽  
Wide Field ◽  
Loop Control ◽  
Dopant Activation ◽  
Integrated Circuit Fabrication ◽  
Metal Silicides ◽  
Circuit Fabrication ◽  
Infrared Lamps

ABSTRACTThermal processing in silicon integrated circuit fabrication steps for dopant activation, metal silicides, annealing, and oxidation commonly uses single-wafer furnaces that rapidly heat wafers with incandescent infrared lamps. Radiation pyrometers and thermocouple probes are the principle methods of measuring wafer temperature for closed-loop control of rapid thermal processes. The challenge with thermocouples is in dealing with heat from the lamps and non-ideal thermally resistive wafer contact. The challenge with pyrometry is in compensating for the variable emissivity of wafer surfaces and suppressing interference from the lamps. Typical deposited or grown layers of silicon nitride, silicon dioxide, and polycrystalline silicon can produce dramatic changes in emissivity. Layer thicknesses and composition are generally not known with sufficient accuracy, so a method for real time in situ emissivity compensation is required. Accufiber introduced a “ripple technique” to address this issue. The idea is to use two probes, separately sensing radiation from the wafer and the lamps, and extracting AC and quasi-DC parts from each. The AC signals provide a measure of the reflectivity of the wafer, and thence emissivity, as well as the fraction of reflected lamp radiation present in the DC signals. Lucent Technologies introduced a method of using AC lamp ripple to measure wafer temperatures with two radiation probes at a wall in the furnace. One probe views radiation emanating from the wafer through a gap in the lamp array. The other probe has a wide field of view to include lamp radiation. The accuracy of Lucent devices, determined from process results on wafers with various emissivities, is typically in the range of 12°C to 18°C at three standard deviations.

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