Optimization for SEU/SET Immunity on 0.15 $\mu$m Fully Depleted CMOS/SOI Digital Logic Devices

2006 ◽  
Vol 53 (6) ◽  
pp. 3422-3427 ◽  
Author(s):  
A. Makihara ◽  
T. Yamaguchi ◽  
H. Asai ◽  
Y. Tsuchiya ◽  
Y. Amano ◽  
...  
Keyword(s):  
Digital Logic ◽  
Fully Depleted ◽  
Logic Devices

Hardness-by-design approach for 0.15 /spl mu/m fully depleted CMOS/SOI digital logic devices with enhanced SEU/SET immunity

2005 ◽  
Vol 52 (6) ◽  
pp. 2524-2530 ◽  
Author(s):  
A. Makihara ◽  
M. Midorikawa ◽  
T. Yamaguchi ◽  
Y. Iide ◽  
T. Yokose ◽  
...  
Keyword(s):  
Design Approach ◽  
Digital Logic ◽  
Fully Depleted ◽  
Logic Devices

RESEARCH OF THE OPERATION PRINCIPLE OF OF THE MULTIPLEXER AND DEMULTIPLEXER USING MODERN PEDAGOGICAL TRAINING TECHNOLOGIES

2021 ◽  
Vol 73 (1) ◽  
pp. 96-102
Author(s):  
D.A. Kinzhebayeva ◽  
◽  
A.S. Kinzhebayeva ◽  
Keyword(s):  
Lesson Plan ◽  
Digital Logic ◽  
Educational Institutions ◽  
Learning Technology ◽  
Teaching Techniques ◽  
Higher Educational Institutions ◽  
Logic Devices ◽  
Pedagogical Training ◽  
Higher Educational ◽  
Basic Learning

This article presents a methodological technology for studying digital logic devices. Recommendations on the technology of teaching digital logic devices using rational, best methodological methods and teaching techniques are given. The proposed topic is "Multiplexer and demultiplexer". Studying methods used: modular studying, developmental studying, demonstration (frontal), step-by-step studying, problem-based studying. The process of implementing learning technology explained by the plan prepared for the lesson (mostly the basics of electronics in Kazakhstan are not included into the educational basis of the school and are only taught in higher educational institutions, therefore, the basic learning range, conventionally referred to in the lesson plan, seminars or lectures.

Study of RF Coupling Behaviour of Digital Logic Devices

1992 ◽  
Vol 9 (6) ◽  
pp. 414-418
Author(s):  
G K Deb ◽  
Manik Mukherjee ◽  
P Suresh Kumar
Keyword(s):  
Digital Logic ◽  
Logic Devices

Digital Logic Design

2009 ◽  
Author(s):  
Guy Even ◽  
Moti Medina
Keyword(s):  
Digital Logic ◽  
Logic Design

Improvement of Single-Electron Digital Logic Gates by Utilizing Input Discretizers

2016 ◽  
Vol E99.C (2) ◽  
pp. 285-292 ◽  
Author(s):  
Tran THI THU HUONG ◽  
Hiroshi SHIMADA ◽  
Yoshinao MIZUGAKI
Keyword(s):  
Logic Gates ◽  
Single Electron ◽  
Digital Logic
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