An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA

2018 ◽  
Vol 67 (2) ◽  
pp. 406-414 ◽  
Author(s):  
Jie Zhang ◽  
Dongming Zhou
Keyword(s):  
Delay Line ◽  
Digital Converter ◽  
Two Stage ◽  
Time To Digital Converter

scholarly journals Two-Stage Clock-Free Time-to-Digital Converter Based on Vernier and Tapped Delay Lines in FPGA Device

Electronics ◽  
2021 ◽  
Vol 10 (18) ◽  
pp. 2190
Author(s):  
Ryszard Szplet ◽  
Arkadiusz Czuba
Keyword(s):  
Integrated Circuit ◽  
Delay Line ◽  
Measurement Range ◽  
Clock Signal ◽  
Test Results ◽  
Digital Converter ◽  
Two Stage ◽  
Time To Digital Converter ◽  
Programmable Device ◽  
Metrological Parameters

This article presents an idea, design and test results of a new time-to-digital converter (TDC) implemented in an FPGA device. The high resolution of 13 ps and measurement range of 3.4 ns are achieved based on a two-stage time interpolation (TI). In the first and second stages of the TI we have used the Vernier delay line and a single tapped delay line, respectively. This solution provides respectable metrological parameters without the need to use a clock signal, and significantly saves the logical resources of an integrated circuit (IC). The proposed method, generally based on two different variants of the discrete delay line, is easy to design and implement in digital ICs. For experimental verification, the TDC was implemented in a single programmable device from family Virtex-7 (Xilinx).

A Low-Power High-Linear Time-to-Digital Converter for Measuring R-R Intervals in ECG Signal Optimized by Neural Network and TLBO Algorithm

2018 ◽  
Vol 28 (02) ◽  
pp. 1950021
Author(s):  
B. Ghanavati ◽  
E. Abiri ◽  
M. R. Salehi ◽  
N. Azhdari
Keyword(s):  
Neural Network ◽  
Dynamic Range ◽  
Linear Time ◽  
Optimization Method ◽  
Cmos Technology ◽  
Time Interval ◽  
Digital Converter ◽  
Two Stage ◽  
Time To Digital Converter ◽  
Tlbo Algorithm

In this paper, a two-stage time interpolation time-to-digital converter (TDC) is proposed to achieve adequate resolution and wide dynamic range for measuring R-R intervals in QRS detection. The architecture is based on a coarse counter and a couple of two-stage interpolator circuit in order to improve the conversion linearity. The proposed TDC is modeled with the neural network, while the teacher–learner-based optimization algorithm (TLBO) is used to optimize the integral nonlinearity (INL) of the proposed TDC. The proposed optimization method shows a characteristic close to the ideal output of the TDC behavior over a wide input range. Using the achieved results of the TLBO algorithm simulation results using CADENCE VIRTUOSO and standard 180[Formula: see text]nm CMOS technology shows 1.2[Formula: see text]s dynamic range, 100[Formula: see text]ns resolution, 0.19[Formula: see text]mW power consumption and area of 0.16[Formula: see text]mm2. The proposed circuit can find application in biomedical engineering systems and other fields where long and accurate time interval measurement is needed.

A 9 Bit, 3.6 ps Resolution Pipeline Time-to-Digital Converter

2019 ◽  
Vol 29 (08) ◽  
pp. 2050124
Author(s):  
Farshad Goodarzi ◽  
Siroos Toofan
Keyword(s):  
Fine Structure ◽  
Delay Line ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Digital Converter ◽  
Time Intervals ◽  
Wide Linear Range ◽  
Time To Digital Converter ◽  
Good Linearity ◽  
Time Amplifier

This paper describes a 9-bit time-to-digital converter (TDC) with 3.6 ps resolution. The resolution of 3.6 ps is achieved using coarse and fine structure. The structure of the proposed two-step pipeline TDC is composed of a 4-bit coarse TDC (CTDC) based on delay line and a 5-bit fine TDC (FTDC) based on an SAR-CD algorithm where a Time Amplifier (TA) is used between them. Since TA amplifies the time intervals in different stages of delay line to achieve accurate gain with wide linear range. Therefore, the TDC has good linearity. The proposed TDC has Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) errors of 1.6 and 2.6 LSB, respectively. This TDC was designed in 0.18[Formula: see text][Formula: see text]m CMOS technology. Using a supply voltage of 1.8[Formula: see text]V, the proposed TDC consumes 1.88[Formula: see text]mW at 25 MS/s throughput.

scholarly journals All-digital ΔΣ time-to-digital converter with bi-directional gated delay line time integrator

2021 ◽  
Author(s):  
Parth Parekh
Keyword(s):  
Delay Line ◽  
Building Blocks ◽  
Cmos Technology ◽  
Time Variable ◽  
Noise Shaping ◽  
Digital Converter ◽  
First Order ◽  
Time To Digital Converter ◽  
Oversampling Ratio ◽  
Signal Band

This report presents a low-power time integrator and its applications in an all-digital first-order ΔΣ time-to-digital converter (TDC). Time-to-Digital Converter (TDC) that map a time variable to a digital code is the most important building blocks of time-mode circuits. The time integrator is realized using a bi-directional gated delay line (BD-GDL) with time variable to be integrated as the gating signal. The integration of the time variable is obtained via the accumulation of the charge of the load capacitor and the logic state of gated delay stages. Issues affecting the performance of the time integrator and TDC are examined. The all-digital first-order ΔΣ TDC utilizing the time integrator was designed in using IBM 130 nm 1.2 V CMOS technology and analysed using Spectre ASP from Cadence Design Systems with BSIM4 models. A sinusoid time input of 333 ps amplitude and 231 kHz frequency with an oversampling ratio 68 was digitized by the modulator. The TDC provides first-order noise-shaping and a SNR of 34.64 dB over the signal band 48.27 ~ 231 kHz while consuming 293.8 μW.

scholarly journals All-digital ΔΣ time-to-digital converter with bi-directional gated delay line time integrator

2021 ◽  
Author(s):  
Parth Parekh
Keyword(s):  
Delay Line ◽  
Building Blocks ◽  
Cmos Technology ◽  
Time Variable ◽  
Noise Shaping ◽  
Digital Converter ◽  
First Order ◽  
Time To Digital Converter ◽  
Oversampling Ratio ◽  
Signal Band

This report presents a low-power time integrator and its applications in an all-digital first-order ΔΣ time-to-digital converter (TDC). Time-to-Digital Converter (TDC) that map a time variable to a digital code is the most important building blocks of time-mode circuits. The time integrator is realized using a bi-directional gated delay line (BD-GDL) with time variable to be integrated as the gating signal. The integration of the time variable is obtained via the accumulation of the charge of the load capacitor and the logic state of gated delay stages. Issues affecting the performance of the time integrator and TDC are examined. The all-digital first-order ΔΣ TDC utilizing the time integrator was designed in using IBM 130 nm 1.2 V CMOS technology and analysed using Spectre ASP from Cadence Design Systems with BSIM4 models. A sinusoid time input of 333 ps amplitude and 231 kHz frequency with an oversampling ratio 68 was digitized by the modulator. The TDC provides first-order noise-shaping and a SNR of 34.64 dB over the signal band 48.27 ~ 231 kHz while consuming 293.8 μW.

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