Cascading delay line time-to-digital converter with 75 ps resolution and a reduced number of delay cells

This paper describes a 9-bit time-to-digital converter (TDC) with 3.6 ps resolution. The resolution of 3.6 ps is achieved using coarse and fine structure. The structure of the proposed two-step pipeline TDC is composed of a 4-bit coarse TDC (CTDC) based on delay line and a 5-bit fine TDC (FTDC) based on an SAR-CD algorithm where a Time Amplifier (TA) is used between them. Since TA amplifies the time intervals in different stages of delay line to achieve accurate gain with wide linear range. Therefore, the TDC has good linearity. The proposed TDC has Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) errors of 1.6 and 2.6 LSB, respectively. This TDC was designed in 0.18[Formula: see text][Formula: see text]m CMOS technology. Using a supply voltage of 1.8[Formula: see text]V, the proposed TDC consumes 1.88[Formula: see text]mW at 25 MS/s throughput.

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Impact of NBTI induced variations on FinFET based Vernier delay line time to digital converter

2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2) ◽

10.1109/icnets2.2017.8067912 ◽

2017 ◽

Author(s):

S. R. Sriram ◽

B. Bindu

Keyword(s):

Delay Line ◽

Digital Converter ◽

Time To Digital Converter

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All-digital ΔΣ time-to-digital converter with bi-directional gated delay line time integrator

10.32920/ryerson.14663841 ◽

2021 ◽

Author(s):

Parth Parekh

Keyword(s):

Delay Line ◽

Building Blocks ◽

Cmos Technology ◽

Time Variable ◽

Noise Shaping ◽

Digital Converter ◽

First Order ◽

Time To Digital Converter ◽

Oversampling Ratio ◽

Signal Band

This report presents a low-power time integrator and its applications in an all-digital first-order ΔΣ time-to-digital converter (TDC). Time-to-Digital Converter (TDC) that map a time variable to a digital code is the most important building blocks of time-mode circuits. The time integrator is realized using a bi-directional gated delay line (BD-GDL) with time variable to be integrated as the gating signal. The integration of the time variable is obtained via the accumulation of the charge of the load capacitor and the logic state of gated delay stages. Issues affecting the performance of the time integrator and TDC are examined. The all-digital first-order ΔΣ TDC utilizing the time integrator was designed in using IBM 130 nm 1.2 V CMOS technology and analysed using Spectre ASP from Cadence Design Systems with BSIM4 models. A sinusoid time input of 333 ps amplitude and 231 kHz frequency with an oversampling ratio 68 was digitized by the modulator. The TDC provides first-order noise-shaping and a SNR of 34.64 dB over the signal band 48.27 ~ 231 kHz while consuming 293.8 μW.

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All-digital ΔΣ time-to-digital converter with bi-directional gated delay line time integrator

10.32920/ryerson.14663841.v1 ◽

2021 ◽

Author(s):

Parth Parekh

Keyword(s):

Delay Line ◽

Building Blocks ◽

Cmos Technology ◽

Time Variable ◽

Noise Shaping ◽

Digital Converter ◽

First Order ◽

Time To Digital Converter ◽

Oversampling Ratio ◽

Signal Band

This report presents a low-power time integrator and its applications in an all-digital first-order ΔΣ time-to-digital converter (TDC). Time-to-Digital Converter (TDC) that map a time variable to a digital code is the most important building blocks of time-mode circuits. The time integrator is realized using a bi-directional gated delay line (BD-GDL) with time variable to be integrated as the gating signal. The integration of the time variable is obtained via the accumulation of the charge of the load capacitor and the logic state of gated delay stages. Issues affecting the performance of the time integrator and TDC are examined. The all-digital first-order ΔΣ TDC utilizing the time integrator was designed in using IBM 130 nm 1.2 V CMOS technology and analysed using Spectre ASP from Cadence Design Systems with BSIM4 models. A sinusoid time input of 333 ps amplitude and 231 kHz frequency with an oversampling ratio 68 was digitized by the modulator. The TDC provides first-order noise-shaping and a SNR of 34.64 dB over the signal band 48.27 ~ 231 kHz while consuming 293.8 μW.

Download Full-text