Die-Level Vacuum Packaging of Mems Devices with Non-Evaporating Getters

In this article original method of vacuum packaging in ceramic package 5142.48-A with non-evaporating getter inside is described. Some MEMS devices such as gyroscopes, accelerometers and resonators often require high and stable vacuum for operational capability. It is known two main approaches to the vacuum packaging of MEMS devices: hermetization on the wafer level and on the die level. Die-level vacuum packaging can be implemented by sealing the die in ceramic package providing excellent hermeticity with sufficiently low leak rate. However, because of outgassing from materials of the package it is difficult to achieve stable vacuum over all MEMS device lifetime. To prevent vacuum degradation it is necessary to use special materials that can remove active gases from the package by chemical sorption named getters. In this work tablet-shaped non-evaporating getter with thickness of 0.7 mm made of titan-vanadium alloy with activation temperature near 525 °C was used. For the vacuum packaging workflow new special vacuum chamber is designed. It may contain four MEMS devices simultaneously. During the process of getter activation heating was provided by halogen lamps G12 35 Wplaced over the caps of the ceramic packages with a little gap. It is defined that in deep vacuum full power of one lamp can heat the cap of the package to the temperature more than 600 °C. Probable overheating is excluded by means of the newly-designed programmable device — power switch, which can maintain required temperature in automatic mode for the necessary time. Temperature control is realized by no-contact pyrometrical method. During the experiment all necessary parameters providing specified temperature profile of the process were determined. Efficiency of the developed vacuum packaging workflow is successfully confirmed by the high and stable Q-factor of fabricated MEMS gyroscopes.

Two-Stage Clock-Free Time-to-Digital Converter Based on Vernier and Tapped Delay Lines in FPGA Device

This article presents an idea, design and test results of a new time-to-digital converter (TDC) implemented in an FPGA device. The high resolution of 13 ps and measurement range of 3.4 ns are achieved based on a two-stage time interpolation (TI). In the first and second stages of the TI we have used the Vernier delay line and a single tapped delay line, respectively. This solution provides respectable metrological parameters without the need to use a clock signal, and significantly saves the logical resources of an integrated circuit (IC). The proposed method, generally based on two different variants of the discrete delay line, is easy to design and implement in digital ICs. For experimental verification, the TDC was implemented in a single programmable device from family Virtex-7 (Xilinx).

Intelligent Network Layer for Cyber-Physical Systems Security

The cyber-physical system (CPS) has made tremendous progress in recent years and also disrupting technical fields ranging from health, transportation, industries, and more. However, CPS security is still one of the concerns for wide adoption owing to the high number of devices connecting to the internet and the traditional security solutions may not be suitable to protect the advanced, application-specific attacks. This paper presents a programmable device network layer architecture to combat attacks and efficient network monitoring in heterogeneous environment CPS applications. The authors leverage industrial control systems (ICS) to discuss the existing issues, highlighting the importance of advanced network layers for CPS. The programmable data plane language (P4) is introduced to detect well known HELLO flood attacks with minimal effort in the network level and show that programmable switches are suitable to implement security solutions in CPS applications.

Expert System for Aerial Vehicle Deployment System Selection

An expert system is a programmable device developed to provide automation for engineering problem solving. It is composed of artificial intelligence modules, subroutine functions, and databases. Under this framework, a design process is proposed to assist the conceptual design of aerial vehicles' deployment systems. The problem is first defined by a set of design requirements for take-off, landing, and cruise. The values are then translated to a set of performance parameters needed for the design process via a newly developed parametric search algorithm. Such parameters are categorised by a fuzzy inference module to determine the most suitable deployment-propulsion system, for conventional and V/STOL vehicles. Through the use of linear and neural network regression, a number of aerodynamic terms are estimated to support flight mechanics analyses, where the optimal take-off and landing thrust vectors are determined. Engine specifications are deduced in terms of unit thrust, weight, bypass ratio and dimension. The design process demonstrates effectiveness in sizing engines for V/STOL operations.

Expert System for Aerial Vehicle Deployment System Selection

An expert system is a programmable device developed to provide automation for engineering problem solving. It is composed of artificial intelligence modules, subroutine functions, and databases. Under this framework, a design process is proposed to assist the conceptual design of aerial vehicles' deployment systems. The problem is first defined by a set of design requirements for take-off, landing, and cruise. The values are then translated to a set of performance parameters needed for the design process via a newly developed parametric search algorithm. Such parameters are categorised by a fuzzy inference module to determine the most suitable deployment-propulsion system, for conventional and V/STOL vehicles. Through the use of linear and neural network regression, a number of aerodynamic terms are estimated to support flight mechanics analyses, where the optimal take-off and landing thrust vectors are determined. Engine specifications are deduced in terms of unit thrust, weight, bypass ratio and dimension. The design process demonstrates effectiveness in sizing engines for V/STOL operations.

Field-Programmable Gate Array

Field-programmable gate arrays (FPGAs) are integrated circuits whose logic and their interconnections are configurable. These devices are field-programmable, that is, they can be configured by the hardware designer without any intervention of the manufacturer. Most FPGAs can be reprogrammed as many times as we want with a vast variety of digital circuits. Some recent FPGA families are system-on-chips (SoC) with one or more microprocessor cores, memory, cache, and reconfigurable logic allowing the implementation of complex hardware/software systems in a single programmable device. This article focuses on the architecture of FPGAs, including the so called SoC FPGA. It explains the main blocks of the FPGA, how they have evolved along the last decades and the perspectives of next generation FPGAs. It also describes some applicability areas and how its architecture have evolved to adapt to some of these target markets.

Multicarrier multimodulation techniques in multilevel neutral point clamped inverter setup for advanced power electronics and drives lab

A laboratory setup is developed to experimentally reinforce the student’s understanding of multilevel neutral point clamped inverter operated with various multicarrier and modulation reference signals. Sixteen combinations of carrier and reference signals out of many more possible are studied in this setup. The lab module is project-based and is designed to perform experiments for the ‘advanced power electronics and drives’ course at the undergraduate level. The hardware implementation details of the multilevel inverter are given in detail for reference to the teachers, students and researchers. Flexible hardware able to be driven by an analogue pulse-generation circuit is explained here or by an external digital programmable device is developed. With the help of dSPACE, complex reference signals are produced for performance analysis.

Electro-actuated valves and self-vented channels enable programmable flow control and monitoring in capillary-driven microfluidics

Microfluidics are essential for many lab-on-a-chip applications, but it is still challenging to implement a portable and programmable device that can perform an assay protocol autonomously when used by a person with minimal training. Here, we present a versatile concept toward this goal by realizing programmable liquid circuits where liquids in capillary-driven microfluidic channels can be controlled and monitored from a smartphone to perform various advanced tasks of liquid manipulation. We achieve this by combining electro-actuated valves (e-gates) with passive capillary valves and self-vented channels. We demonstrate the concept by implementing a 5-mm-diameter microfluidic clock, a chip to control four liquids using 100 e-gates with electronic feedback, and designs to deliver and merge multiple liquids sequentially or in parallel in any order and combination. This concept is scalable, compatible with high-throughput manufacturing, and can be adopted in many microfluidics-based assays that would benefit from precise and easy handling of liquids.