A new approach to reducing power dissipation in thermistor probe for temperature/frequency converter based on astable multivibrator

1982 ◽  
Vol IM-31 (4) ◽  
pp. 278-279 ◽  
Author(s):  
Anwar A. Khan ◽  
R. Sengupta
Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Ali Majeed ◽  
Esam Alkaldy

Purpose This study aims to replace current multi-layer and coplanar wire crossing methods in QCA technology to avoid fabrication difficulties caused by them. Design/methodology/approach Quantum-dot cellular automata (QCA) is one of the newly emerging nanoelectronics technology tools that is proposed as a good replacement for complementary metal oxide semiconductor (CMOS) technology. This technology has many challenges, among them being component interconnection and signal routing. This paper will propose a new wire crossing method to enhance layout use in a single layer. The presented method depends on the central cell clock phase to enable two signals to cross over without interference. QCADesigner software is used to simulate a full adder circuit designed with the proposed wire crossing method to be used as a benchmark for further analysis of the presented wire crossing approach. QCAPro software is used for power dissipation analysis of the proposed adder. Findings A new cost function is presented in this paper to draw attention to the fabrication difficulties of the technology when designing QCA circuits. This function is applied to the selected benchmark circuit, and the results show good performance of the proposed method compared to others. The improvement is around 59, 33 and 75% compared to the best reported multi-layer wire crossing, coplanar wire crossing and logical crossing, respectively. The power dissipation analysis shows that the proposed method does not cause any extra power consumption in the circuit. Originality/value In this paper, a new approach is developed to bypass the wire crossing problem in the QCA technique.


2015 ◽  
Vol 13 (05) ◽  
pp. 1550038 ◽  
Author(s):  
Pouran Houshmand ◽  
Majid Haghparast

Reversible logic has been recently considered as an interesting and important issue in designing combinational and sequential circuits. The combination of reversible logic and multi-valued logic can improve power dissipation, time and space utilization rate of designed circuits. Only few works have been reported about sequential reversible circuits and almost there are no paper exhibited about quantum ternary reversible counter. In this paper, first we designed 2-qutrit and 3-qutrit quantum reversible ternary up-counters using quantum ternary reversible T-flip-flop and quantum reversible ternary gates. Then we proposed generalized quantum reversible ternary n-qutrit up-counter. We also introduced a new approach for designing any type of n-qutrit ternary and reversible counter. According to the results, we can conclude that applying second approach quantum reversible ternary up-counter is better than the others.


2004 ◽  
Vol 12 (12) ◽  
pp. 1374-1377 ◽  
Author(s):  
M. Olivieri ◽  
F. Pappalardo ◽  
G. Visalli

2016 ◽  
Vol 2016 ◽  
pp. 1-14 ◽  
Author(s):  
Miquel L. Alomar ◽  
Vincent Canals ◽  
Nicolas Perez-Mora ◽  
Víctor Martínez-Moll ◽  
Josep L. Rosselló

Hardware implementation of artificial neural networks (ANNs) allows exploiting the inherent parallelism of these systems. Nevertheless, they require a large amount of resources in terms of area and power dissipation. Recently, Reservoir Computing (RC) has arisen as a strategic technique to design recurrent neural networks (RNNs) with simple learning capabilities. In this work, we show a new approach to implement RC systems with digital gates. The proposed method is based on the use of probabilistic computing concepts to reduce the hardware required to implement different arithmetic operations. The result is the development of a highly functional system with low hardware resources. The presented methodology is applied to chaotic time-series forecasting.


Sensors ◽  
2020 ◽  
Vol 20 (22) ◽  
pp. 6480
Author(s):  
Timothy C. A. Molteno

A new approach to GPS positioning is described in which the post-processing of ultra-short sequences of captured GPS signal data can produce an estimate of receiver location. The algorithm, called ‘FastFix’, needs only 2–4 ms of stored L1-band data sampled at ∼16 MHz. The algorithm uses a least-squares optimization to estimate receiver position and GPS time from measurements of the relative codephase, and Doppler-shift of GNSS satellite signals. A practical application of this algorithm is demonstrated in a small, lightweight, low-power tracking tag that periodically wakes-up, records and stores 4 ms of GPS L1-band signal and returns to a low-power state—reducing power requirements by a factor of ∼10,000 compared to typical GPS devices. Stationary device testing shows a median error of 27.7 m with a small patch antenna. Results from deployment of this tag on adult Royal Albatross show excellent performance, demonstrating lightweight, solar-powered, long-term tracking of these remarkable birds. This work was performed on the GPS system; however, the algorithm is applicable to other GNSS systems.


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