scholarly journals Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling

2014 ◽  
Author(s):  
Shanghang Zhang ◽  
Xin Li ◽  
R. D. Blanton ◽  
Jose Machado da Silva ◽  
John M. Carulli ◽  
...  
Keyword(s):  
Spatial Variation ◽  
Cost Reduction ◽  
Bayesian Model ◽  
Rf Circuits ◽  
Wafer Level ◽  
Test Cost ◽  
Model Fusion ◽  
Test Cost Reduction

Test Cost Reduction Methodology for In-FO Wafer-Level Chip-Scale Package

2016 ◽  
pp. 1-1
Author(s):  
Kai-Li Wang ◽  
Bing-Yang Lin ◽  
Cheng-Wen Wu ◽  
Mincent Lee ◽  
Hao Chen ◽  
...  
Keyword(s):  
Cost Reduction ◽  
Wafer Level ◽  
Test Cost ◽  
Test Cost Reduction ◽  
Chip Scale Package

Reduced-Pin-Count BOST for Test-Cost Reduction

2021 ◽  
pp. 1-1
Author(s):  
Youngkwang Lee ◽  
Young-woo Lee ◽  
Sungyoul Seo ◽  
Sungho Kang
Keyword(s):  
Cost Reduction ◽  
Test Cost ◽  
Test Cost Reduction

scholarly journals Identifying the Optimal Subsets of Test Items through Adaptive Test for Cost Reduction of ICs

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 680
Author(s):  
Huaguo Liang ◽  
Jinlei Wan ◽  
Tai Song ◽  
Wangchao Hou
Keyword(s):  
Integrated Circuits ◽  
Cost Reduction ◽  
Bayesian Model ◽  
Test Methods ◽  
Test Time ◽  
Test Quality ◽  
Test Cost ◽  
Test Items ◽  
Adaptive Test ◽  
Test Escapes

With the growing complexity of integrated circuits (ICs), more and more test items are required in testing. However, the large number of invalid items (which narrowly pass the test) continues to increase the test time and, consequently, test costs. Aiming to address the problems of long test time and reduced test item efficiency, this paper presents a method which combines a fast correlation-based filter (FCBF) and a weighted naive Bayesian model which can identify the most effective items and make accurate quality predictions. Experimental results demonstrate that the proposed method reduces test time by around 2.59% and leads to fewer test escapes compared with the recently adopted test methods. The study shows that the proposed method can effectively reduce the test cost without jeopardizing test quality excessively.

Reliable test architecture with test cost reduction for systolic based DNN accelerators

2021 ◽  
pp. 1-1
Author(s):  
Muhammad Ibtesam ◽  
Umair Saeed Solangi ◽  
Jinuk Kim ◽  
Muhammad Adil Ansari ◽  
Sungju Park
Keyword(s):  
Cost Reduction ◽  
Test Cost ◽  
Reliable Test ◽  
Test Cost Reduction ◽  
Test Architecture

scholarly journals A scan disabling-based BAST scheme for test cost reduction

2011 ◽  
Vol 8 (16) ◽  
pp. 1367-1373 ◽  
Author(s):  
Zhiqiang You ◽  
Weizheng Wang ◽  
Zhiping Dou ◽  
Peng Liu ◽  
Jishun Kuang
Keyword(s):  
Cost Reduction ◽  
Test Cost ◽  
Test Cost Reduction
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