Drain Current Saturation in Line Tunneling-Based TFETs: An Analog Design Perspective

2018 ◽  
Vol 65 (1) ◽  
pp. 322-330 ◽  
Author(s):  
Abhishek Acharya ◽  
Abhishek B. Solanki ◽  
Sudeb Dasgupta ◽  
Bulusu Anand
2009 ◽  
Vol 23 (12n13) ◽  
pp. 2647-2654 ◽  
Author(s):  
C. STAMPFER ◽  
E. SCHURTENBERGER ◽  
F. MOLITOR ◽  
J. GÜTTINGER ◽  
T. IHN ◽  
...  

We report on electronic transport experiments on a graphene single electron transistor as function of a perpendicular magnetic field. The device, which consists of a graphene island connected to source and drain electrodes via two narrow graphene constrictions is electronically characterized and the device exhibits a characteristic charging energy of approx. 3.5 meV. We investigate the homogeneity of the two graphene "tunnel" barriers connecting the single electron transistor to source and drain contacts as function of laterally applied electric fields, which are also used to electrostatically tune the overall device. Further, we focus on the barrier transparency as function of an applied perpendicular magnetic field and we find an increase of transparency for increasing magnetic field and a source-drain current saturation for magnetic fields exceeding 5 T.


2005 ◽  
Vol 49 (8) ◽  
pp. 1251-1254 ◽  
Author(s):  
M. Balucani ◽  
V.N. Dobrovolsky ◽  
A.V. Osipov ◽  
A. Ferrari

Author(s):  
Gary Pennington ◽  
S. Potbhare ◽  
Neil Goldsman ◽  
D.B. Habersat ◽  
Aivars J. Lelis ◽  
...  

NANO ◽  
2010 ◽  
Vol 05 (03) ◽  
pp. 161-165 ◽  
Author(s):  
A. BENFDILA ◽  
S. ABBAS ◽  
R. IZQUIERDO ◽  
R. TALMAT ◽  
A. VASEASHTA

Electronic devices based on carbon nanotubes (CNTs) show potential for circuit miniaturization due to their superior electrical characteristics and reduced dimensionality. The CNT field effect transistors (CNFETs) offer breakthrough in miniaturization of various electronic circuits. Investigation of ballistic transport governing the operation of CNFETs is essential for understanding the device's functional behavior. This investigation is focused on a study of current–voltage characteristics of device behavior in hard saturation region. The investigation utilizes a set of current–voltage characteristics obtained on typical devices. This work is an extension of our earlier work describing application of our approach to Si -MOSFET behavior in the saturation region.


2006 ◽  
Vol 37 (7) ◽  
pp. 635-641 ◽  
Author(s):  
A. Benfdila ◽  
F. Balestra

2018 ◽  
Vol 11 (14) ◽  
pp. 2198-2203
Author(s):  
Vineet Unni ◽  
Hong Yao Long ◽  
Hongyang Yan ◽  
Akira Nakajima ◽  
Hiroji Kawai ◽  
...  

2004 ◽  
Vol 830 ◽  
Author(s):  
Eisuke Tokumitsu ◽  
Takaaki Miyasako ◽  
Masaru Senoo

ABSTRACTWe report ferroelectric-gate thin film transistors (TFTs) using indium tin oxide (ITO) as a channel material. Bottom-gate structure TFTs have been fabricated using ferroelectric Pb(Zr, Ti)O3 (PZT) film as a gate insulator and ITO channel. Ferroelectric and ITO layers were formed by the sol-gel technique and RF sputtering, respectively. Drain current-drain voltage (ID-VD) characteristics of PZT/ITO ferroelectric-gate TFTs exhibit typical n-channel transistor operations with clear current saturation and electrical properties were improved by the post annealing. Drain current-gate voltage (ID-VG) characteristics demonstrate clear counterclockwise hysteresis loop due to the ferroelectric gate insulator. The obtained memory window is 2 V. The on/off current ratio of more than 102 has been obtained, which indicates that the ITO channel is sufficiently depleted by the ferroelectric polarization.


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