scholarly journals Erratum: Corrigendum: Improved Drain Current Saturation and Voltage Gain in Graphene–on–Silicon Field Effect Transistors

2016 ◽  
Vol 6 (1) ◽  
Author(s):  
Seung Min Song ◽  
Jae Hoon Bong ◽  
Wan Sik Hwang ◽  
Byung Jin Cho
2016 ◽  
Vol 6 (1) ◽  
Author(s):  
Seung Min Song ◽  
Jae Hoon Bong ◽  
Wan Sik Hwang ◽  
Byung Jin Cho

Abstract Graphene devices for radio frequency (RF) applications are of great interest due to their excellent carrier mobility and saturation velocity. However, the insufficient current saturation in graphene field effect transistors (FETs) is a barrier preventing enhancements of the maximum oscillation frequency and voltage gain, both of which should be improved for RF transistors. Achieving a high output resistance is therefore a crucial step for graphene to be utilized in RF applications. In the present study, we report high output resistances and voltage gains in graphene-on-silicon (GoS) FETs. This is achieved by utilizing bare silicon as a supporting substrate without an insulating layer under the graphene. The GoSFETs exhibit a maximum output resistance of 2.5 MΩ∙μm, maximum intrinsic voltage gain of 28 dB, and maximum voltage gain of 9 dB. This method opens a new route to overcome the limitations of conventional graphene-on-insulator (GoI) FETs and subsequently brings graphene electronics closer to practical usage.


NANO ◽  
2010 ◽  
Vol 05 (03) ◽  
pp. 161-165 ◽  
Author(s):  
A. BENFDILA ◽  
S. ABBAS ◽  
R. IZQUIERDO ◽  
R. TALMAT ◽  
A. VASEASHTA

Electronic devices based on carbon nanotubes (CNTs) show potential for circuit miniaturization due to their superior electrical characteristics and reduced dimensionality. The CNT field effect transistors (CNFETs) offer breakthrough in miniaturization of various electronic circuits. Investigation of ballistic transport governing the operation of CNFETs is essential for understanding the device's functional behavior. This investigation is focused on a study of current–voltage characteristics of device behavior in hard saturation region. The investigation utilizes a set of current–voltage characteristics obtained on typical devices. This work is an extension of our earlier work describing application of our approach to Si -MOSFET behavior in the saturation region.


Nano Letters ◽  
2012 ◽  
Vol 12 (3) ◽  
pp. 1324-1328 ◽  
Author(s):  
B. N. Szafranek ◽  
G. Fiori ◽  
D. Schall ◽  
D. Neumaier ◽  
H. Kurz

ACS Nano ◽  
2014 ◽  
Vol 9 (1) ◽  
pp. 363-370 ◽  
Author(s):  
Chris M. Corbet ◽  
Connor McClellan ◽  
Amritesh Rai ◽  
Sushant Sudam Sonde ◽  
Emanuel Tutuc ◽  
...  

1987 ◽  
Vol 65 (5) ◽  
pp. 1072-1078 ◽  
Author(s):  
Paul G. Glavina ◽  
D. Jed Harrison

The fabrication of ion sensitive field effect transistors (ISFET) and microelectrode arrays for use as chemical sensors using a commercial CMOS fabrication process is described. The commercial technology is readily available through the Canadian Microelectronics Corporation; however, several of the recommended design rules must be ignored in preparing chemical sensors using this process. The ISFET devices show near theoretical response to K+ in aqueous solution (55 mV slope) when coated with a K+ sensitive membrane. An extended gate ion sensitive device is presented which offers advantages in encapsulation of ISFET sensors. The source-drain current of both devices show a linear response to log [Formula: see text] in contrast to ISFETs previously reported that have high internal lead resistances. Al and poly-Si microelectrode arrays are fabricated commercially and then Pt is electrodeposited on the microelectrodes. The resulting arrays show good cyclic voltammetric response to Fe(CN)64− and Ru(NH3)63+ and are relatively durable.


2002 ◽  
Vol 743 ◽  
Author(s):  
Z. Y. Fan ◽  
J. Li ◽  
J. Y. Lin ◽  
H. X. Jiang ◽  
Y. Liu ◽  
...  

ABSTRACTThe fabrication and characterization of AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs) with the δ-doped barrier are reported. The incorporation of the SiO2 insulated-gate and the δ-doped barrier into HFET structures reduces the gate leakage and improves the 2D channel carrier mobility. The device has a high drain-current-driving and gate-control capabilities as well as a very high gate-drain breakdown voltage of 200 V, a cutoff frequency of 15 GHz and a maximum frequency of oscillation of 34 GHz for a gate length of 1 μm. These characteristics indicate a great potential of this structure for high-power-microwave applications.


2008 ◽  
Vol 1 ◽  
pp. 061801 ◽  
Author(s):  
Kouji Suemori ◽  
Misuzu Taniguchi ◽  
Sei Uemura ◽  
Manabu Yoshida ◽  
Satoshi Hoshino ◽  
...  

2014 ◽  
Vol 53 (4S) ◽  
pp. 04EC11 ◽  
Author(s):  
Takashi Matsukawa ◽  
Yongxun Liu ◽  
Kazuhiko Endo ◽  
Junichi Tsukada ◽  
Hiromi Yamauchi ◽  
...  

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1493
Author(s):  
Sang-Kon Kim

Although extreme ultraviolet lithography (EUVL) has potential to enable 5-nm half-pitch resolution in semiconductor manufacturing, it faces a number of persistent challenges. Line-edge roughness (LER) is one of critical issues that significantly affect critical dimension (CD) and device performance because LER does not scale along with feature size. For LER creation and impacts, better understanding of EUVL process mechanism and LER impacts on fin-field-effect-transistors (FinFETs) performance is important for the development of new resist materials and transistor structure. In this paper, for causes of LER, a modeling of EUVL processes with 5-nm pattern performance was introduced using Monte Carlo method by describing the stochastic fluctuation of exposure due to photon-shot noise and resist blur. LER impacts on FinFET performance were investigated using a compact device method. Electric potential and drain current with fin-width roughness (FWR) based on LER and line-width roughness (LWR) were fluctuated regularly and quantized as performance degradation of FinFETs.


2001 ◽  
Vol 665 ◽  
Author(s):  
A. Ullmann ◽  
J. Ficker ◽  
W. Fix ◽  
H. Rost ◽  
W. Clemens ◽  
...  

ABSTRACTIntegrated plastic circuits (IPCs) will become an integral component of future low cost electronics. For low cost processes IPCs have to be made of all-polymer Transistors. We present our recent results on fabrication of Organic Field-Effect Transistors (OFETs) and integrated inverters. Top-gate transistors were fabricated using polymer semiconductors and insulators. The source-drain structures were defined by standard lithography of Au on a flexible plastic film, and on top of these electrodes, poly(3-alkylthiophene) (P3AT) as semiconductor, and poly(4-hydroxystyrene) (PHS) as insulator were homogeneously deposited by spin-coating. The gate electrodes consist of metal contacts. With this simple set-up, the transistors exhibit excellent electric performance with a high source-drain current at source - drain and gate voltages below 30V. The characteristics show very good saturation behaviour for low biases and are comparable to results published for precursor pentacene. With this setup we obtain a mobility of 0.2cm2/Vs for P3AT. Furthermore, we discuss organic integrated inverters exhibiting logic capability. All devices show shelf-lives of several months without encapsulation.


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