Considerations for Static Energy Reduction in Digital CMOS ICs Using NEMS Power Gating

2017 ◽  
Vol 64 (3) ◽  
pp. 1399-1403 ◽  
Author(s):  
Sivaneswaran Sankar ◽  
Ulayil Sajesh Kumar ◽  
Mayank Goel ◽  
Maryam Shojaei Baghini ◽  
Valipe Ramgopal Rao
Keyword(s):  
Energy Reduction ◽  
Power Gating ◽  
Digital Cmos ◽  
Static Energy

scholarly journals Hybrid Non-Volatile Flip-Flops Using Spin-Orbit-Torque (SOT) Magnetic Tunnel Junction Devices for High Integration and Low Energy Power-Gating Applications

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1406
Author(s):  
Jaeyoung Park
Keyword(s):  
Tunnel Junction ◽  
Magnetic Tunnel Junction ◽  
Low Energy ◽  
The Other ◽  
Energy Reduction ◽  
Power Gating ◽  
Spin Orbit ◽  
Flip Flop ◽  
Area Overhead ◽  
Nmos Transistors

This paper presents two novel hybrid non-volatile flip-flops (NVFFs) comprised of the conventional CMOS flip-flop for static storage in normal operations and Spin-Orbit-Torque Magnetic Tunnel Junction (SOT-MTJ) devices for temporary storage during power gating. The proposed NVFFs re-utilize a part of the standard CMOS flip-flop infrastructure for storing and restoring data onto MTJs for reducing the area. Furthermore, the proposed NVFFs re-use a write current, which is used for storing an MTJ, to write the other MTJ at a time, resulting in 50% storing energy reduction. To reduce the area further, the number of external terminals of an MTJ is reduced by shorting the shorting physical terminals. Removing a terminal using the proposed STT-Like SOT configuration results in fewer transistors to control. The proposed NVFF circuits are evaluated using a compact MTJ model targeting implementation in a 14-nm technology node. Analysis indicates that area overheads are only 10.3% and 6.9% compared to the conventional D flip-flop because three or two minimum-sized NMOS transistors are added for accessing MTJs. Compared to the best previously known NVFFs, the proposed NVFF has an improvement by a factor of 2–8 in terms of the area overhead.

A Fast Reactivation Scheme in Power Gating Design

2011 ◽  
Vol 135-136 ◽  
pp. 1134-1139
Author(s):  
Ping Huang ◽  
Hui Yuan Xing ◽  
Xian Ju Yang ◽  
Pei Xiang Yan ◽  
Tian Lei Zhao ◽  
...  
Keyword(s):  
Leakage Power ◽  
Energy Reduction ◽  
Power Gating ◽  
Delay Reduction ◽  
Leakage Reduction ◽  
Delay Cost ◽  
Transition Delay ◽  
The Cost

Power gating has become a popular technique to reduce the ever-increasing leakage power for commercial microprocessors or SoCs, however the wakeup energy and delay cost harm its performance. This paper proposes a fast reactivation scheme to reduce the transition delay and energy. The experiment results show that, comparing to the traditional power gating implementation, it can achieve 19.66% reactivation energy reduction, 9.28% peak leakage reduction, and 23.36% wakeup delay reduction, at the cost of 2.75% area increasing.

Static energy reduction techniques for microprocessor caches

2003 ◽  
Vol 11 (3) ◽  
pp. 303-313 ◽  
Author(s):  
H. Hanson ◽  
M.S. Hrishikesh ◽  
V. Agarwal ◽  
S.W. Keckler ◽  
D. Burger
Keyword(s):  
Energy Reduction ◽  
Reduction Techniques ◽  
Static Energy
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