Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits

2008 ◽  
Author(s):  
Enrico Macii ◽  
Leticia Bolzani ◽  
Andrea Calimera ◽  
Alberto Macii ◽  
Massimo Poncino
Keyword(s):  
Power Optimization ◽  
Leakage Power ◽  
Cmos Circuits ◽  
Power Gating ◽  
Clock Gating ◽  
Digital Cmos

Power Optimization Using Clock Gating and Power Gating

2016 ◽  
pp. 1-20
Author(s):  
Arsalan Shahid ◽  
Saad Arif ◽  
Muhammad Yasir Qadri ◽  
Saba Munawar
Keyword(s):  
Power Optimization ◽  
Cmos Technology ◽  
Optimization Techniques ◽  
Power Gating ◽  
Clock Gating ◽  
Dynamic Voltage ◽  
Significant Performance ◽  
Operand Isolation ◽  
Increasing Demand ◽  
And Performance

The scaling of CMOS technology has continued due to ever increasing demand of greater performance with low power consumption. This demand has grown further by the portable and battery operated devices market. To meet the challenge of greater energy efficiency and performance, a number of power optimization techniques at processor and system components level are proposed by the research community such as clock gating, operand isolation, memory splitting, power gating, dynamic voltage and frequency scaling, etc. This chapter reviews advancements in the dynamic power optimization techniques like clock gating and power gating. This chapter also reviews some architectures and optimization techniques that have been developed for greater power reduction without any significant performance degradation or area cost.

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