Charge Trapping Model for Temporal Threshold Voltage Shift in a-IGZO TFTs Considering Variations of Carrier Density in Channel and Electric Field in Gate Insulator

2015 ◽  
Vol 62 (7) ◽  
pp. 2219-2225 ◽  
Author(s):  
Lisa Ling Wang ◽  
Hongyu He ◽  
Xiang Liu ◽  
Wei Deng ◽  
Shengdong Zhang
Keyword(s):  
Electric Field ◽  
Threshold Voltage ◽  
Carrier Density ◽  
Charge Trapping ◽  
Gate Insulator ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Trapping Model

The Use of C-V Techniques To Investigate Instability Mechanisms in M-I-S Structures

2002 ◽  
Vol 716 ◽  
Author(s):  
S. Paul ◽  
W.I Milne ◽  
J. Robertson
Keyword(s):  
Threshold Voltage ◽  
Chemical Vapour ◽  
Charge Trapping ◽  
Gate Insulator ◽  
Gate Bias ◽  
Major Drawback ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Chemical Vapour Deposition Technique ◽  
Mis Structures

AbstractIn the field of flat panel displays, the current leading technology is the Active Matrix liquid Crystal Display; this uses a-Si:H based thin film transistors (TFTs) as the switching element in each pixel. However, under gate bias a-Si:H TFTs suffer from instability, as is evidenced by a shift in the gate threshold voltage. The shift in the gate threshold voltage is generally measured from the gate transfer characteristics, after subjecting the TFT to prolonged gate bias. However, a major drawback of this measurement method is that it cannot distinguish whether the shift is caused by the change in the midgap states in the a-Si:H channel or by charge trapping in the gate insulator. In view of this, we have developed a capacitance-voltage (C-V) method to measure the shift in threshold voltage. We employ Metal-Insulator-Semiconductor (MIS) structures to investigate the threshold voltage shift as they are simpler to fabricate than TFTs. We have investigated a large of number Metal/a-Si:H/Si3N4/Si+n structures using our C-V technique. From, the C-V data for the MIS structures, we have found that the relationship between the thermal energy and threshold voltage shift is similar to that reported by Wehrspohn et. al in a-Si:H TFTs (J Appl. Phys, 144, 87, 2000). The a-Si:H and Si3N4 layers were grown using the radiofrequency plasma-enhanced chemical vapour deposition technique.

scholarly journals Analysis of Threshold Voltage Shift for Full VGS/VDS/Oxygen-Content Span under Positive Bias Stress in Bottom-Gate Amorphous InGaZnO Thin-Film Transistors

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 327
Author(s):  
Je-Hyuk Kim ◽  
Jun Tae Jang ◽  
Jong-Ho Bae ◽  
Sung-Jin Choi ◽  
Dong Myong Kim ◽  
...  
Keyword(s):  
Thin Film ◽  
Electric Field ◽  
Oxygen Content ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Electron Trapping ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Drain Side ◽  
Bottom Gate

In this study, we analyzed the threshold voltage shift characteristics of bottom-gate amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) under a wide range of positive stress voltages. We investigated four mechanisms: electron trapping at the gate insulator layer by a vertical electric field, electron trapping at the drain-side GI layer by hot-carrier injection, hole trapping at the source-side etch-stop layer by impact ionization, and donor-like state creation in the drain-side IGZO layer by a lateral electric field. To accurately analyze each mechanism, the local threshold voltages of the source and drain sides were measured by forward and reverse read-out. By using contour maps of the threshold voltage shift, we investigated which mechanism was dominant in various gate and drain stress voltage pairs. In addition, we investigated the effect of the oxygen content of the IGZO layer on the positive stress-induced threshold voltage shift. For oxygen-rich devices and oxygen-poor devices, the threshold voltage shift as well as the change in the density of states were analyzed.

COMPARATIVE INSTABILITIES ANALYSIS FOR a-Si:H BODY-TIED TFT (BT-TFT) AND FLOATING BODY TFT (FB-TFT) UNDER BIAS TEMPERATURE STRESSING (BTS)

2008 ◽  
Vol 22 (05) ◽  
pp. 337-341
Author(s):  
YONG K. LEE ◽  
SUNG-HOON CHOA
Keyword(s):  
Silicon Nitride ◽  
Threshold Voltage ◽  
Gate Insulator ◽  
Floating Body ◽  
Negative Bias ◽  
Positive Bias ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Bias Stress ◽  
Hole Trapping

The a- Si:H thin film transistors TFT with silicon nitride as a gate insulator have been stressed with negative and positive bias to realize the instability mechanisms. With proposed BT-TFT and FB-TFT devices, it is found that the threshold voltages of both BT-TFT and BT-TFT devices are positively shifted under positive bias stress and then negatively shifted for negative bias stress. The positive threshold voltage shift is due to the electron trapping in the silicon nitride or at the a- Si:H /silicon nitride interface. The negative threshold voltage shift is mainly due to hole trapping and/or electron de-trapping in the silicon nitride or at the a- Si:H /silicon nitride interface. The positive or negative threshold voltage shift keeps increasing with increasing positive or negative gate bias for both BT-TFT and FB-TFT devices. However, as far as the threshold voltage shift slope is concerned, under positive bias stress, both BT-TFT and FB-TFT devices are similar to each other. On the other hand, under negative bias stress, BT-TFT shift amount is much less than one for the FB-TFT device.

Investigation on the Electrical Stability of 5,11-Bis(triethylsilylethynyl)anthradithiophene Thin-Film Transistors

2021 ◽  
Vol 21 (3) ◽  
pp. 1754-1760
Author(s):  
Joel Ndikumana ◽  
Jyothi Chintalapalli ◽  
Jin-Hyuk Kwon ◽  
Jin-Hyuk Bae ◽  
Jaehoon Park
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Ambient Air ◽  
Gate Insulator ◽  
Hydroxyl Groups ◽  
Electrical Stability ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Domain Boundaries

We investigate the effects of environmental conditions on the electrical stability of spin-coated 5,11-bis(triethylsilylethynyl)anthradithiophene (TES-ADT) thin-film transistors (TFTs) in which crosslinked poly(4-vinylphenol-co-methyl methacrylate) (PVP-co-PMMA) was utilized as a gate insulator layer. Atomic force microscopy observations show molecular terraces with domain boundaries in the spin-coated TEST-ADT semiconductor film. The TFT performance was observed to be superior in the ambient air condition. Under negative gate-bias stress, the TES-ADT TFTs showed a positive threshold voltage shift in ambient air and a negative threshold voltage shift under vacuum. These results are explained through a chemical reaction between water molecules in air and unsubstituted hydroxyl groups in the cross-linked PVP-co-PMMA as well as a charge-trapping phenomenon at the domain boundaries in the spin-coated TES-ADT semiconductor.

Fabrication of 0.1 µm channel diamond Metal-Insulator-Semiconductor Field-Effect Transistor

2001 ◽  
Vol 680 ◽  
Author(s):  
Hitoshi Umezawa ◽  
Yoshikazu Ohba ◽  
Hiroaki Ishizaka ◽  
Takuya Arima ◽  
Hirotada Taniuchi ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Gate Insulator ◽  
Short Channel ◽  
Threshold Voltage Shift ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
Voltage Shift ◽  
Effect Transistor

ABSTRACTAnalysis of diamond short channel effect is carried out for the first time. 70 nm channel diamond metal-insulator semiconductor field-effect transistor is realized by utilizing new FET fabrication process on the hydrogen-terminated surface conductive layer. This FET is the shortest gate length in diamond FETs. FETs with thick gate insulator of 35 nm show significant threshold voltage shift and degradation of subthreshold slope S by the gate refining. This phenomenon occurs due to the penetration of drain field into channel. However, the degradation of subthreshold performance and threshold voltage shift are hardly observed in 0.17 µm FET with thin gate insulator 15 nm in thickness.

Unusual Threshold Voltage Shift Caused by Self-Heating-Induced Charge Trapping Effect

2010 ◽  
Vol 13 (4) ◽  
pp. H95
Author(s):  
Fu-Yen Jian ◽  
Ting-Chang Chang ◽  
An-Kuo Chu ◽  
Te-Chih Chen ◽  
Shih-Ching Chen ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Charge Trapping ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Self Heating ◽  
Trapping Effect ◽  
Induced Charge

Analysis of threshold voltage shift of pentacene field effect transistor with ferroelectric gate insulator as a Maxwell–Wagner effect

2008 ◽  
Vol 516 (9) ◽  
pp. 2753-2757 ◽  
Author(s):  
Ryousuke Tamura ◽  
Eunju Lim ◽  
Shuhei Yoshita ◽  
Takaaki Manaka ◽  
Mitsumasa Iwamoto
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Gate Insulator ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Effect Transistor

scholarly journals Hysteresis Reduction for Organic Thin Film Transistors with Multiple Stacked Functional Zirconia Polymeric Films

Crystals ◽  
2019 ◽  
Vol 9 (12) ◽  
pp. 634 ◽  
Author(s):  
Kwon ◽  
Choi ◽  
Bae ◽  
Park
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistor ◽  
Charge Trapping ◽  
Polymeric Films ◽  
Gate Insulator ◽  
Organic Thin Film ◽  
Threshold Voltage Shift ◽  
Gate Insulators ◽  
Temperature Solution

We show that transfer hysteresis for a pentacene thin film transistor (TFT) with a low-temperature solution-processed zirconia (ZrOx) gate insulator can be remarkably reduced by modifying the ZrOx surface with a thin layer of crosslinked poly(4-vinylphenol) (c-PVP). Pentacene TFTs with bare ZrOx and c-PVP stacked ZrOx gate insulators were fabricated, and their hysteresis behaviors compared. The different gate insulators exhibited no significant surface morphology or capacitance differences. The threshold voltage shift magnitude decreased by approximately 71% for the TFT with the c-PVP stacked ZrOx gate insulator compared with the bare ZrOx gate insulator, with 0.75 ± 0.05 and 0.22 ± 0.03 V threshold voltage shifts for the bare ZrOx and c-PVP stacked ZrOx gate insulators, respectively. The hysteresis reduction was attributed to effectively covering hysteresis-inducing charge trapping sites on ZrOx surfaces.

scholarly journals Charge Trapping by Self-Assembled Monolayers as the Origin of the Threshold Voltage Shift in Organic Field-Effect Transistors

Small ◽  
2011 ◽  
Vol 8 (2) ◽  
pp. 241-245 ◽  
Author(s):  
Fatemeh Gholamrezaie ◽  
Anne-Marije Andringa ◽  
W. S. Christian Roelofs ◽  
Alfred Neuhold ◽  
Martijn Kemerink ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Charge Trapping ◽  
Self Assembled Monolayers ◽  
Organic Field Effect Transistors ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Assembled Monolayers ◽  
Self Assembled
Sign in / Sign up

Export Citation Format

Share Document