Interface Trap Density of Gate-All-Around Silicon Nanowire Field-Effect Transistors With TiN Gate: Extraction and Compact Model

2013 ◽  
Vol 60 (8) ◽  
pp. 2457-2463 ◽  
Author(s):  
Faraz Najam ◽  
Yun Seop Yu ◽  
Keun Hwi Cho ◽  
Kyoung Hwan Yeo ◽  
Dong-Won Kim ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Trap Density ◽  
Compact Model ◽  
Interface Trap Density ◽  
Interface Trap

scholarly journals Interface trap density and mobility extraction in InGaAs buried quantum well metal-oxide-semiconductor field-effect-transistors by gated Hall method

2014 ◽  
Vol 104 (13) ◽  
pp. 131605 ◽  
Author(s):  
Thenappan Chidambaram ◽  
Dmitry Veksler ◽  
Shailesh Madisetti ◽  
Andrew Greene ◽  
Michael Yakimov ◽  
...  
Keyword(s):  
Quantum Well ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Trap Density ◽  
Oxide Semiconductor ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Hall Method

Effect of NH3 Post-Oxidation Annealing on Flatness of SiO2/SiC Interface

2013 ◽  
Vol 740-742 ◽  
pp. 723-726 ◽  
Author(s):  
Narumasa Soejima ◽  
Taishi Kimura ◽  
Tsuyoshi Ishikawa ◽  
Takahide Sugiyama
Keyword(s):  
Nitrous Oxide ◽  
Field Effect ◽  
Inversion Layer ◽  
Trap Density ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Field Effect Mobility ◽  
Interfacial Roughness ◽  
Cross Sectional ◽  
Mos Capacitors

We investigated the effects of the post-oxidation annealing (POA) atmosphere on the electrical properties and interfacial roughness of SiO2 deposited on a 4H-SiC (0001) face and SiC. POA in ammonia (NH3) gave MOS capacitors with a lower interface trap density and n-channel MOSFETs with higher field-effect mobility than POA in nitrous oxide (N2O) or nitrogen (N2). In contrast, POA in N2O gave a lower interface trap density than POA in N2, but it gave the lowest field-effect mobility of all the samples. Cross-sectional TEM observations revealed that N2O POA gave a higher interfacial roughness than NH3 POA. We thus considered that N2O POA degraded the inversion-layer mobility due to increased roughness scattering.

A Relationship between Interface Trap Density and Transconductance in 6H-SiC Enhancement Mode Field Effect Transistors

1995 ◽  
Vol 410 ◽  
Author(s):  
M. W. Dryfuse ◽  
M. Tabib-Azar
Keyword(s):  
Experimental Data ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Interface Traps ◽  
Pertinent Literature ◽  
Enhancement Mode ◽  
Mode Field ◽  
Simplifying Assumptions

ABSTRACTAn explicit analytical expression relating the interface trap densities and transconductance is derived for enhancement mode field effect transistors without any simplifying assumptions regarding the energy distribution of traps. Using this relationship, the interface trap densities were calculated from transconductance data and compared to experimental data and that provided in the literature. Our expression provides a simple and convenient method to reliably estimate interface traps densities from the readily available transconductance data provided in the pertinent literature.

scholarly journals Simulation studies on electrical characteristics of silicon nanowire feedback field-effect transistors with interface trap charges

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Yejin Yang ◽  
Young-Soo Park ◽  
Jaemin Son ◽  
Kyoungah Cho ◽  
Sangsig Kim
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Drain Current ◽  
Memory Window ◽  
Interface Trap ◽  
Electrical Characteristics ◽  
The Difference ◽  
Trap Charges

AbstractIn this study, we examine the electrical characteristics of silicon nanowire feedback field-effect transistors (FBFETs) with interface trap charges between the channel and gate oxide. The band diagram, I–V characteristics, memory window, and operation were analyzed using a commercial technology computer-aided design simulation. In an n-channel FBFET, the memory window narrows (widens) from 5.47 to 3.59 V (9.24 V), as the density of the positive (negative) trap charges increases. In contrast, in the p-channel FBFET, the memory window widens (narrows) from 5.38 to 7.38 V (4.18 V), as the density of the positive (negative) trap charges increases. Moreover, we investigate the difference in the output drain current based on the interface trap charges during the memory operation.

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