Electrical Properties of Low-Temperature-Compatible P-Channel Polycrystalline-Silicon TFTs Using High-$\kappa$ Gate Dielectrics

2008 ◽  
Vol 55 (4) ◽  
pp. 1027-1034 ◽  
Author(s):  
Ming-Jui Yang ◽  
Chao-Hsin Chien ◽  
Yi-Hsien Lu ◽  
Chih-Yen Shen ◽  
Tiao-Yuan Huang
2006 ◽  
Vol 89 (24) ◽  
pp. 242902 ◽  
Author(s):  
K. Ramani ◽  
C. R. Essary ◽  
S. Y. Son ◽  
V. Craciun ◽  
R. K. Singh

1992 ◽  
Vol 284 ◽  
Author(s):  
Y. Ma ◽  
T. Yasuda ◽  
Y. L. Chen ◽  
G. Lucovsky ◽  
D. M. Maher

ABSTRACTOxide-Nitride-Oxide, ONO, heterostructures, fabricated by low-temperature, 300°C, Remote Plasma Enhanced Chemical Vapor Deposition, have been used as gate dielectrics in metal insulator semiconductor devices. Analysis of C-V data for this devices indicates that higher levels of fixed charge are associated with the internal dielectric interfaces. A high-temperature, ̃900°C, Rapid Thermal Annealing, RTA, step has been inserted into the process sequence for fabricating ultra-thin, 4.7 nm SiO2 equivalent, device-quality ONO dielectric layers. The electrical properties of these ONO dielectrics, including the Si/SiO2 interfacial trap density, the flat band voltage, the charge to breakdown and the reliability under electron injection are comparable to those of high temperature, thermally-grown oxides.


1992 ◽  
Author(s):  
Huang-Chung Cheng ◽  
Jau-Jey Wang ◽  
Ya-Hsiang Tai ◽  
Ming Shiann Feng

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