Off-State Current and Performance Analysis for Double-Gate CMOS With Non-Self-Aligned Back Gate

K. Kim; H.I. Hanafi; J. Cai; C.-T. Chuang

doi:10.1109/ted.2005.854292

Off-State Current and Performance Analysis for Double-Gate CMOS With Non-Self-Aligned Back Gate

IEEE Transactions on Electron Devices ◽

10.1109/ted.2005.854292 ◽

2005 ◽

Vol 52 (9) ◽

pp. 2104-2107

Author(s):

K. Kim ◽

H.I. Hanafi ◽

J. Cai ◽

C.-T. Chuang

Keyword(s):

Performance Analysis ◽

Double Gate ◽

Back Gate ◽

And Performance

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Design and Performance Analysis of Proposed Biosensor based on Double Gate Junctionless Transistor

Silicon ◽

10.1007/s12633-021-01335-6 ◽

2021 ◽

Author(s):

Pawandeep Kaur ◽

Avtar Singh Buttar ◽

Balwinder Raj

Keyword(s):

Performance Analysis ◽

Double Gate ◽

Junctionless Transistor ◽

And Performance

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DC and AC performance analysis of 25 nm symmetric/asymmetric double-gate, back-gate and bulk CMOS

2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502) ◽

10.1109/sispad.2000.871229 ◽

2002 ◽

Cited By ~ 10

Author(s):

MeiKei Ieong ◽

H.-S.P. Wong ◽

Yuan Taur ◽

P. Oldiges ◽

D. Frank

Keyword(s):

Performance Analysis ◽

Double Gate ◽

Back Gate

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Compact 2D threshold voltage modeling and performance analysis of ternary metal alloy work-function-engineered double-gate MOSFET

Journal of Computational Electronics ◽

10.1007/s10825-017-1015-6 ◽

2017 ◽

Vol 16 (3) ◽

pp. 648-657 ◽

Cited By ~ 10

Author(s):

Priyanka Saha ◽

Saheli Sarkhel ◽

Subir Kumar Sarkar

Keyword(s):

Performance Analysis ◽

Work Function ◽

Threshold Voltage ◽

Metal Alloy ◽

Double Gate ◽

Double Gate Mosfet ◽

Ternary Metal ◽

And Performance

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Modelling and performance analysis of asymmetric double gate stack-oxide junctionless FET in subthreshold region

2017 IEEE Region 10 Humanitarian Technology Conference (R10-HTC) ◽

10.1109/r10-htc.2017.8289017 ◽

2017 ◽

Author(s):

Md. Shafiqul Islam ◽

Jannatul Afza ◽

Sanjida Tarannum

Keyword(s):

Performance Analysis ◽

Double Gate ◽

Gate Stack ◽

Subthreshold Region ◽

And Performance

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Self-consistent Optimization and Performance Analysis of Double-Gate MOS Transistors

30th European Solid-State Device Research Conference ◽

10.1109/essderc.2000.194783 ◽

2000 ◽

Cited By ~ 1

Author(s):

S. Monfray ◽

J.L. Autran ◽

M. Jurczak ◽

T. Skotnicki

Keyword(s):

Performance Analysis ◽

Double Gate ◽

Mos Transistors ◽

Self Consistent ◽

And Performance ◽

Optimization And Performance

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Design and performance analysis of A Triple Material Double Gate Cylindrical Gate All Around (TMDG CGAA) MOSFET in Nano-meter Regime

SKIT Research Journal ◽

10.47904/ijskit.10.2.2020.27-33 ◽

2020 ◽

Vol 10 (2) ◽

pp. 27

Author(s):

Asmita Menaria ◽

Rahul Pandey

Keyword(s):

Performance Analysis ◽

Double Gate ◽

And Performance

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Analytical modeling and performance analysis for symmetric double gate stack-oxide junctionless field effect transistor in subthreshold region

2017 IEEE Region 10 Humanitarian Technology Conference (R10-HTC) ◽

10.1109/r10-htc.2017.8288963 ◽

2017 ◽

Cited By ~ 2

Author(s):

Raisa Fabiha ◽

Chinmoy Nath Saha ◽

Md. Shafiqul Islam

Keyword(s):

Performance Analysis ◽

Field Effect ◽

Analytical Modeling ◽

Field Effect Transistor ◽

Double Gate ◽

Gate Stack ◽

Subthreshold Region ◽

Effect Transistor ◽

And Performance

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Design and performance analysis of double-gate MOSFET over single-gate MOSFET for RF switch

Microelectronics Journal ◽

10.1016/j.mejo.2010.12.007 ◽

2011 ◽

Vol 42 (3) ◽

pp. 527-534 ◽

Cited By ~ 35

Author(s):

Viranjay M. Srivastava ◽

K.S. Yadav ◽

G. Singh

Keyword(s):

Performance Analysis ◽

Double Gate ◽

Rf Switch ◽

Double Gate Mosfet ◽

And Performance

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Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch

Microelectronics Journal ◽

10.1016/j.mejo.2011.07.003 ◽

2011 ◽

Vol 42 (10) ◽

pp. 1124-1135 ◽

Cited By ~ 40

Author(s):

Viranjay M. Srivastava ◽

K.S. Yadav ◽

G. Singh

Keyword(s):

Performance Analysis ◽

Double Gate ◽

Rf Switch ◽

Double Gate Mosfet ◽

And Performance

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Analytical Modelling and Performance Analysis of Dielectric Pocket-Induced Double-Gate Tunnel Field-Effect Transistor

IETE Technical Review ◽

10.1080/02564602.2017.1381049 ◽

2017 ◽

Vol 36 (1) ◽

pp. 17-26 ◽

Cited By ~ 4

Author(s):

Priyanka Saha ◽

Tripty Kumari ◽

Subir Kumar Sarkar

Keyword(s):

Performance Analysis ◽

Field Effect ◽

Field Effect Transistor ◽

Analytical Modelling ◽

Double Gate ◽

Effect Transistor ◽

Tunnel Field Effect Transistor ◽

And Performance

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