Statistical simulation of leakage currents in mos and flash memory devices with a new multiphonon trap-assisted tunneling model

2003 ◽  
Vol 50 (5) ◽  
pp. 1246-1253 ◽  
Author(s):  
L. Larcher
Keyword(s):  
Flash Memory ◽  
Statistical Simulation ◽  
Memory Devices ◽  
Leakage Currents ◽  
Tunneling Model ◽  
Trap Assisted Tunneling ◽  
Assisted Tunneling

Quantitative analysis of SILCs (stress-induced leakage currents) based on the inelastic trap-assisted tunneling model

1999 ◽  
Author(s):  
Shiro Kamohara ◽  
Yutaka Okuyama ◽  
Yukiko Manabe ◽  
Kosuke Okuyama ◽  
Katsuhiko Kubota ◽  
...  
Keyword(s):  
Quantitative Analysis ◽  
Leakage Currents ◽  
Tunneling Model ◽  
Trap Assisted Tunneling ◽  
Assisted Tunneling

APPLICATION OF EPITAXIAL UNIPOLAR BARRIERS TO REDUCE NOISE CURRENTS IN PHOTODETECTORS

2011 ◽  
Vol 20 (03) ◽  
pp. 557-564
Author(s):  
G. R. SAVICH ◽  
J. R. PEDRAZZANI ◽  
S. MAIMON ◽  
G. W. WICKS
Keyword(s):  
Leakage Current ◽  
Surface Passivation ◽  
Leakage Currents ◽  
Type Region ◽  
Surface Leakage Current ◽  
Unipolar Barrier ◽  
Trap Assisted Tunneling ◽  
Assisted Tunneling ◽  
Tunneling Currents ◽  
Surface Leakage

Tunneling currents and surface leakage currents are both contributors to the overall dark current which limits many semiconductor devices. Surface leakage current is generally controlled by applying a post-epitaxial passivation layer; however, surface passivation is often expensive and ineffective. Band-to-band and trap assisted tunneling currents cannot be controlled through surface passivants, thus an alternative means of control is necessary. Unipolar barriers, when appropriately applied to standard electronic device structures, can reduce the effects of both surface leakage and tunneling currents more easily and cost effectively than other methods, including surface passivation. Unipolar barriers are applied to the p -type region of a conventional, MBE grown, InAs based pn junction structures resulting in a reduction of surface leakage current. Placing the unipolar barrier in the n -type region of the device, has the added benefit of reducing trap assisted tunneling current as well as surface leakage currents. Conventional, InAs pn junctions are shown to exhibit surface leakage current while unipolar barrier photodiodes show no detectable surface currents.

I - V Characteristics in Surface-Activated Bonding (SAB) Based Si/SiC Junctions at Raised Ambient Temperatures

2014 ◽  
Vol 778-780 ◽  
pp. 718-721 ◽  
Author(s):  
Shota Nishida ◽  
Jian Bo Liang ◽  
Masashi Morimoto ◽  
Naoteru Shigekawa ◽  
Manabu Arai
Keyword(s):  
Electron Microscopy ◽  
Scanning Electron Microscopy ◽  
Electrical Properties ◽  
Reverse Bias ◽  
Tunneling Model ◽  
Ambient Temperatures ◽  
Current Voltage ◽  
Trap Assisted Tunneling ◽  
Assisted Tunneling ◽  
Scanning Electron

The physical and electrical properties of p+-Si/n-4H-SiC and n+-Si/n-4H-SiC heterojunctions fabricated by using surface-activated bonding (SAB) were investigated by scanning electron microscopy (SEM), current-voltage (I-V) and breakdown characteristics measurements at raised ambient temperatures. The I-V characteristics for the reverse bias voltages of the two junctions were compared with the expectations based on Frenkel-Poole, and trap-assisted tunneling models. The results of calculations using the trap-assisted tunneling model were close to the measurements.

scholarly journals Compact Trap-Assisted-Tunneling Model for Line Tunneling Field-Effect-Transistor Devices

2020 ◽  
Vol 10 (13) ◽  
pp. 4475
Author(s):  
Faraz Najam ◽  
Yun Seop Yu
Keyword(s):  
Experimental Data ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Potential Profile ◽  
Relaxation Energy ◽  
Tunneling Model ◽  
Compact Formulation ◽  
Trap Assisted Tunneling ◽  
Assisted Tunneling

Trap-assisted-tunneling (TAT) is a well-documented source of severe subthreshold degradation in tunneling field-effect-transistors (TFET). However, the literature lacks in numerical or compact TAT models applied to TFET devices. This work presents a compact formulation of the Schenk TAT model that is used to fit experimental drain-source current (Ids) versus gate-source voltage (Vgs) data of an L-shaped and line tunneling type TFET. The Schenk model incorporates material-dependent fundamental physical constants that play an important role in influencing the TAT generation (GTAT) including the lattice relaxation energy, Huang–Rhys factor, and the electro-optical frequency. This makes fitting any experimental data using the Schenk model physically relevant. The compact formulation of the Schenk TAT model involved solving the potential profile in the TFET and using that potential profile to calculate GTAT using the standard Schenk model. The GTAT was then approximated by the Gaussian distribution function for compact implementation. The model was compared against technology computer-aided design (TCAD) results and was found in reasonable agreement. The model was also used to fit an experimental device’s Ids–Vgs characteristics. The results, while not exactly fitting the experimental data, follow the general experimental Ids–Vgs trend reasonably well; the subthreshold slope was loosely similar to the experimental device. Additionally, the ON-current, especially to make a high drain-source bias model accurate, can be further improved by including effects such as electrostatic degradation and series resistance.

Resistive memory variability: A simplified trap-assisted tunneling model

2016 ◽  
Vol 115 ◽  
pp. 126-132 ◽  
Author(s):  
Daniele Garbin ◽  
Elisa Vianello ◽  
Quentin Rafhay ◽  
Mourad Azzaz ◽  
Philippe Candelier ◽  
...  
Keyword(s):  
Resistive Memory ◽  
Tunneling Model ◽  
Trap Assisted Tunneling ◽  
Assisted Tunneling
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