scholarly journals Closed-form breakdown voltage model for PD SOI NMOS devices considering impact ionization of both parasitic BJT and surface MOS channel simultaneously

2002 ◽  
Vol 49 (11) ◽  
pp. 2016-2023 ◽  
Author(s):  
Shih-Chia Lin ◽  
J.B. Kuo
Keyword(s):  
Closed Form ◽  
Breakdown Voltage ◽  
Impact Ionization

The Closed-Form Solutions For The Breakdown Voltages Of 6H-SiC Reachthrough Diodes

1998 ◽  
Vol 512 ◽  
Author(s):  
You-Sang Lee ◽  
D.-S. Byeon ◽  
Y.-I. Choi ◽  
I.-Y. Park ◽  
Min-Koo Han
Keyword(s):  
Closed Form ◽  
Breakdown Voltage ◽  
Epitaxial Layer ◽  
Doping Concentration ◽  
Impact Ionization ◽  
Analytic Solutions ◽  
Ionization Coefficient ◽  
Closed Form Solutions ◽  
The Impact ◽  
Effective Ionization

ABSTRACTThe closed-form analytic solutions for the breakdown voltage of 6H-SiC RTD, reachthrough diode, having the structure of p+-n-n+, are successfully derived by solving the impact ionization integral using effective ionization coefficient in the reachthrough condition. In the region of the lowly doped epitaxial layer, the breakdown voltages of 6H-SiC RTD nearly constant with the increased doping concentration. Also the breakdown voltages of 6H-SiC RTD decrease, in the region of the highly doped epitaxial layer, which coincides with Baliga'seq. [1].

Enhancement of Breakdown Voltage in SOI MOSFET Using Buried p-Type Silicon

2021 ◽  
Author(s):  
Deivakani M ◽  
Sumithra M.G ◽  
Anitha P ◽  
Jenopaul P ◽  
Priyesh P. Gandhi ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Impact Ionization ◽  
Semiconductor Industry ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Physical Models ◽  
Oxide Semiconductor ◽  
Soi Mosfet ◽  
P Type ◽  
Conventional Device

Abstract Semiconductor industry is still looking for the enhancement of breakdown voltage in Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Thus, in this paper, heavy n-type doping below the channel is proposed for SOI MOSFET. Simulation of SOI MOSFET is carried out using 2D TCAD physical simulator. In the conventional device, with no p-type doping is used at the bottom silicon layer. While, in proposed device, p-type doping of 1×1018 cm-3 is used. Physical models are used in the simulation to achieve realistic performance. The models are mobility model, impact ionization model and ohmic contact model. Using TCAD simulation, electron/hole current density, impact generation, recombination and breakdown phenomena are analyzed. It is found that the proposed with p-type doping of 1×1018 cm-3 for SOI MOSFET yields high breakdown voltage. In contrast to conventional device, 20% improvement in breakdown voltage is achieved for proposed device.

High Voltage Silicon Carbide Devices

1998 ◽  
Vol 512 ◽  
Author(s):  
B. Jayant Baliga
Keyword(s):  
Silicon Carbide ◽  
Breakdown Voltage ◽  
High Voltage ◽  
Impact Ionization ◽  
Voltage Drop ◽  
Schottky Diodes ◽  
Inversion Layer ◽  
Drift Region ◽  
Edge Termination ◽  
Silicon Devices

ABSTRACTProgress made in the development of high performance power rectifiers and switches from silicon carbide are reviewed with emphasis on approaching the 100-fold reduction in the specific on-resistance of the drift region when compared with silicon devices with the same breakdown voltage. The highlights are: (a) Recently completed measurements of impact ionization coefficients in SiC indicate an even higher Baliga's figure of merit than projected earlier. (b) The commonly reported negative temperature co-efficient for breakdown voltage in SiC devices has been shown to arise at defects, allaying concerns that this may be intrinsic to the material. (c) Based upon fundamental considerations, it has been found that Schottky rectifiers offer superior on-state voltage drop than P-i-N rectifiers for reverse blocking voltages below 3000 volts. (d) Nearly ideal breakdown voltage has been experimentally obtained for Schottky diodes using an argon implanted edge termination. (e) Planar ion-implanted junctions have been successfully fabricated using oxide as a mask with high breakdown voltage and low leakage currents by using a filed plate edge termination. (f) High inversion layer mobility has been experimentally demonstrated on both 6H and 4H-SiC by using a deposited oxide layer as gate dielectric. (g) A novel, high-voltage, normally-off, accumulation-channel, MOSFET has been proposed and demonstrated with 50x lower specific on-resistance than silicon devices in spite of using logic-level gate drive voltages. These results indicate that SiC based power devices could become commercially viable in the 21st century if cost barriers can be overcome.

Temperature Dependence of Impact Ionization Coefficients in 4H-SiC

2014 ◽  
Vol 778-780 ◽  
pp. 461-466 ◽  
Author(s):  
Hiroki Niwa ◽  
Jun Suda ◽  
Tsunenobu Kimoto
Keyword(s):  
Temperature Dependence ◽  
Temperature Coefficient ◽  
Breakdown Voltage ◽  
Elevated Temperatures ◽  
Phonon Scattering ◽  
Impact Ionization ◽  
Negative Temperature ◽  
Positive Temperature Coefficient ◽  
Positive Temperature ◽  
Ionization Coefficients

Impact ionization coefficients of 4H-SiC were measured at room temperature and at elevated temperatures up to 200°C. Photomultiplication measurement was done in two complementary photodiodes to measure the multiplication factors of holes (Mp) and electrons (Mn), and ionization coefficients were extracted. Calculated breakdown voltage using the obtained ionization coefficients showed good agreement with the measured values in this study, and also in other reported PiN diodes and MOSFETs. In high-temperature measurement, breakdown voltage exhibited a positive temperature coefficient and multiplication factors showed a negative temperature coefficient. Therefore, extracted ionization coefficient has decreased which can be explained by the increase of phonon scattering. The calculated temperature dependence of breakdown voltage agreed well with the measured values not only for the diodes in this study, but also in PiN diode in other literature.

Modeling of a Breakdown Voltage in GaN Rectifiers and SiC Rectifiers

2001 ◽  
Vol 680 ◽  
Author(s):  
You-Sang Lee ◽  
Min-Koo Han ◽  
Yearn-Ik Choi
Keyword(s):  
Breakdown Voltage ◽  
Epitaxial Layer ◽  
Doping Concentration ◽  
Impact Ionization ◽  
Accurate Approximation ◽  
Ionization Coefficient ◽  
Zinc Blende ◽  
The Impact

ABSTRACTThe breakdown voltage of wurtzite and zinc-blende GaN rectifiers as function of a doping concentration and the width of epitaxial layer were successfully modeled in the reach-through case. The breakdown voltage was derived by the impact ionization integral employing the effective impact ionization coefficient and an accurate approximation. Our model shows that the breakdown voltage of wurtzite GaN rectifier was larger than those of zinc-blende GaN rectifier and SiC rectifiers including 4H-SiC and 6H-SiC in the condition that both the thickness and doping concentration of epitaxial layer are identical.

Improved Analytical Expressions for Avalanche Breakdown in 4H-SiC

2014 ◽  
Vol 778-780 ◽  
pp. 467-470
Author(s):  
Zachary Stum ◽  
Yi Tang ◽  
Harsh Naik ◽  
T. Paul Chow
Keyword(s):  
Electric Field ◽  
Breakdown Voltage ◽  
Power Law ◽  
Impact Ionization ◽  
Avalanche Breakdown ◽  
Layer Width ◽  
One Dimensional ◽  
Avalanche Breakdown Voltage ◽  
Analytical Expressions ◽  
Better Than

A new power law is approximated for effective impact ionization in 4H-SiC, which is then used to generate one-dimensional equations for critical electric field, avalanche breakdown voltage, and depletion layer width that match both simulation and published device results better than previous published equations.

scholarly journals New Submicron Low Gate Leakage In0.52Al0.48As-In0.7Ga0.3As pHEMT for Low-Noise Applications

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1497
Author(s):  
Mohamed Fauzi Packeer Mohamed ◽  
Mohamad Faiz Mohamed Omar ◽  
Muhammad Firdaus Akbar Jalaludin Khan ◽  
Nor Azlin Ghazali ◽  
Mohd Hendra Hairi ◽  
...  
Keyword(s):  
Band Gap ◽  
Breakdown Voltage ◽  
Impact Ionization ◽  
High Mobility ◽  
High Electron Mobility Transistor ◽  
Low Noise ◽  
Gate Length ◽  
High Electron ◽  
Gate Leakage ◽  
The Impact

Conventional pseudomorphic high electron mobility transistor (pHEMTs) with lattice-matched InGaAs/InAlAs/InP structures exhibit high mobility and saturation velocity and are hence attractive for the fabrication of three-terminal low-noise and high-frequency devices, which operate at room temperature. The major drawbacks of conventional pHEMT devices are the very low breakdown voltage (<2 V) and the very high gate leakage current (∼1 mA/mm), which degrade device and performance especially in monolithic microwave integrated circuits low-noise amplifiers (MMIC LNAs). These drawbacks are caused by the impact ionization in the low band gap, i.e., the InxGa(1−x)As (x = 0.53 or 0.7) channel material plus the contribution of other parts of the epitaxial structure. The capability to achieve higher frequency operation is also hindered in conventional InGaAs/InAlAs/InP pHEMTs, due to the standard 1 μm flat gate length technology used. A key challenge in solving these issues is the optimization of the InGaAs/InAlAs epilayer structure through band gap engineering. A related challenge is the fabrication of submicron gate length devices using I-line optical lithography, which is more cost-effective, compared to the use of e-Beam lithography. The main goal for this research involves a radical departure from the conventional InGaAs/InAlAs/InP pHEMT structures by designing new and advanced epilayer structures, which significantly improves the performance of conventional low-noise pHEMT devices and at the same time preserves the radio frequency (RF) characteristics. The optimization of the submicron T-gate length process is performed by introducing a new technique to further scale down the bottom gate opening. The outstanding achievements of the new design approach are 90% less gate current leakage and 70% improvement in breakdown voltage, compared with the conventional design. Furthermore, the submicron T-gate length process also shows an increase of about 58% and 33% in fT and fmax, respectively, compared to the conventional 1 μm gate length process. Consequently, the remarkable performance of this new design structure, together with a submicron gate length facilitatesthe implementation of excellent low-noise applications.

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