A Low Power and Small Area FFT Processor for OFDM Demodulator

2007 ◽  
Vol 53 (2) ◽  
pp. 274-277 ◽  
Author(s):  
Xiaojin Li ◽  
Zongsheng Lai ◽  
Jianmin Cui
Keyword(s):  
Low Power ◽  
Small Area ◽  
Fft Processor

Performance Analysis of an Area Efficient and Low Power MOD-R2MDC FFT for MIMO OFDM

2014 ◽  
Vol 573 ◽  
pp. 176-180
Author(s):  
G. Kavitha ◽  
B. Kirthiga ◽  
N. Kirubanandasarathy
Keyword(s):  
Low Power ◽  
Orthogonal Frequency Division Multiplexing ◽  
Ofdm System ◽  
Description Language ◽  
Fft Processor ◽  
Synthesis Tool ◽  
Mimo Ofdm ◽  
Hardware Description ◽  
Fft Algorithms ◽  
Area Efficient

In this paper, an area-efficient low power fast fourier transform (FFT) processor is proposed for multi input multi output-orthogonal frequency division multiplexing (MIMO-OFDM) in wireless communication system. It consists of a modified architecture of radix-2 algorithm which is described as modified radix-2 multipath delay commutation (MOD-R2MDC). The OFDM receiver with modified R2MDC (MOD-R2MDC) FFT was designed by Hardware Description Language (HDL) coding The Xilinx ISE Design Suite 10.1 is used as a synthesis tool for getting the power and area. The Model-Sim 6.3c is used for simulation. Also the existing OFDM system has been tested with these FFT algorithms and their performances were analyzed with respect to occupancy area in FPGA and power consumption. A low-power and area efficient architecture enables the real-time operations of MIMO OFDM system.

scholarly journals Low-power, high-speed FFT processor for MB-OFDM UWB application

2011 ◽  
Author(s):  
Guixuan Liang ◽  
Danping He ◽  
Eduardo de la Torre ◽  
Teresa Riesgo
Keyword(s):  
Low Power ◽  
High Speed ◽  
Fft Processor
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