2007 2nd International Design and Test Workshop
Latest Publications

TOTAL DOCUMENTS

73

(FIVE YEARS 0)

H-INDEX

6

(FIVE YEARS 0)

Published By IEEE

9781424418244, 9781424418251

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Optimization of Interacting Controllers Using K-wise Tests

2007 2nd International Design and Test Workshop ◽

10.1109/idt.2007.4437453 ◽

2007 ◽

Author(s):

Sezer Goren

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Multi-cycle Fault Injections in Error Detecting Implementations of the Advanced Encryption Standard

2007 2nd International Design and Test Workshop ◽

10.1109/idt.2007.4437419 ◽

2007 ◽

Author(s):

P. Maistri ◽

R. Leveugle

Keyword(s):

Advanced Encryption Standard ◽

Error Detecting

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A High-Speed, Low-Area Processor Array Architecture for Multiplication and Squaring over GF(2m)

2007 2nd International Design and Test Workshop ◽

10.1109/idt.2007.4437465 ◽

2007 ◽

Cited By ~ 4

Author(s):

Mohamed A. Fayed ◽

M. Watheq El-Kharashi ◽

Fayez Gebali

Keyword(s):

High Speed ◽

Processor Array ◽

Low Area ◽

Array Architecture

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A High Performance ASIC Based Elliptic Curve Cryptographic Processor over GF(p)

2007 2nd International Design and Test Workshop ◽

10.1109/idt.2007.4437455 ◽

2007 ◽

Author(s):

Xiaopeng Zhang ◽

Shuguo Li

Keyword(s):

Elliptic Curve ◽

High Performance

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Low Power Small Area High Performance 2D-DCT architecture

2007 2nd International Design and Test Workshop ◽

10.1109/idt.2007.4437443 ◽

2007 ◽

Cited By ~ 3

Author(s):

M.R.M. Rizk ◽

Mostafa Ammar

Keyword(s):

Low Power ◽

Small Area ◽

High Performance

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Adopting the Scan Approach for a Fault Tolerant Asynchronous Clock Generation Circuit

2007 2nd International Design and Test Workshop ◽

10.1109/idt.2007.4437442 ◽

2007 ◽

Author(s):

T. Handl ◽

A. Steininger ◽

G. Kempf

Keyword(s):

Fault Tolerant ◽

Clock Generation

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Recovery from Transition Errors in Sequential Circuits

2007 2nd International Design and Test Workshop ◽

10.1109/idt.2007.4437439 ◽

2007 ◽

Cited By ~ 1

Author(s):

Ramashis Das ◽

John P. Hayes

Keyword(s):

Sequential Circuits

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A Novel General Graph-Based Simplex Algorithm Applied to IC Layout Compaction and Migration

2007 2nd International Design and Test Workshop ◽

10.1109/idt.2007.4437469 ◽

2007 ◽

Cited By ~ 1

Author(s):

Hazem Said ◽

Hazem M. Abbas ◽

Hussein I. Shahein

Keyword(s):

Simplex Algorithm ◽

General Graph ◽

And Migration

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A Novel Method of Test Generation for Asynchronous Circuits

2007 2nd International Design and Test Workshop ◽

10.1109/idt.2007.4437420 ◽

2007 ◽

Author(s):

Dilip P. Vasudevan

Keyword(s):

Test Generation ◽

Asynchronous Circuits ◽

Novel Method

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Analog, Digital and Mixed-Signal Design Flows

2007 2nd International Design and Test Workshop ◽

10.1109/idt.2007.4437470 ◽

2007 ◽

Cited By ~ 5

Author(s):

Hany G. Bakeer ◽

Omar Shaheen ◽

Haitham M. Eissa ◽

Mohamed Dessouky

Keyword(s):

Signal Design ◽

Mixed Signal

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