Corrections to "Enhancing the reliability of wafer level packaging by using solder joints layout design"

2007 ◽  
Vol 30 (1) ◽  
pp. 190-190
Author(s):  
Chang-Ming Liu ◽  
Chang-Chun Lee ◽  
Kuo-Ning Chiang
Keyword(s):  
Solder Joints ◽  
Layout Design ◽  
Wafer Level ◽  
Wafer Level Packaging

Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology

2007 ◽  
Vol 47 (2-3) ◽  
pp. 196-204 ◽  
Author(s):  
Chang-Chun Lee ◽  
Chien-Chen Lee ◽  
Hsiao-Tung Ku ◽  
Shu-Ming Chang ◽  
Kuo-Ning Chiang
Keyword(s):  
Response Surface Methodology ◽  
Response Surface ◽  
Solder Joints ◽  
Layout Design ◽  
Wafer Level ◽  
Wafer Level Packaging

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

3D IC/Stacked Device Fault Isolation Using 3D Magnetic Field Imaging

2014 ◽  
Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Fault Isolation ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Current Location ◽  
Geometrical Information ◽  
Magnetic Field Imaging ◽  
Silicon Vias ◽  
Non Destructive ◽  
Field Imaging

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

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