CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits

Purpose This paper aims to investigate the strength at interlayer of specimens fabricated using Contour Crafting (CC) to develop a concrete mixture for large-scale three-dimensional printing. Design/methodology/approach The collected data from several experiments were analyzed to understand significant factors and their interactions. After developing the empirical model, condition for maximum desirability was identified and the model was validated. Findings The experimental investigation of varied combination of concrete components introduced an empirical model which can predict the strength at interface. Moreover, an optimized mixture within constrains of the CC nozzle was developed and validated. Originality/value Several experimental samples were tested, and the derived empirical model was validated after more than 600 h of work.

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Design and Implementation of a Large Scale Tree-Based QR Decomposition Using a 3D Virtual Systolic Array and a Lightweight Runtime

Parallel Processing Letters ◽

10.1142/s0129626414420043 ◽

2014 ◽

Vol 24 (04) ◽

pp. 1442004

Author(s):

Ichitaro Yamazaki ◽

Jakub Kurzak ◽

Piotr Luszczek ◽

Jack Dongarra

Keyword(s):

Integrated Circuits ◽

Systolic Array ◽

Large Scale ◽

Three Dimensional ◽

Qr Decomposition ◽

Dense Matrix ◽

Von Neumann ◽

Computing Paradigm ◽

Array Architecture ◽

Von Neumann Architecture

A systolic array provides an alternative computing paradigm to the von Neumann architecture. Though its hardware implementation has failed as a paradigm to design integrated circuits in the past, we are now discovering that the systolic array as a software virtualization layer can lead to an extremely scalable execution paradigm. To demonstrate this scalability, in this paper, we design and implement a 3D virtual systolic array to compute a tile QR decomposition of a tall-and-skinny dense matrix. Our implementation is based on a state-of-the-art algorithm that factorizes a panel based on a tree-reduction. Freed from the constraint of a planar layout, we present a three-dimensional virtual systolic array architecture for this algorithm. Using a runtime developed as a part of the Parallel Ultra Light Systolic Array Runtime (PULSAR) project, we demonstrate on a Cray-XT5 machine how our virtual systolic array can be mapped to a large-scale machine and obtain excellent parallel performance. This is an important contribution since such a QR decomposition is used, for example, to compute a least squares solution of an overdetermined system, which arises in many scientific and engineering problems.

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Some applications of electron beam microanalysis techniques in VLSI process evaluation

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s042482010007463x ◽

1983 ◽

Vol 41 ◽

pp. 160-161

Author(s):

Simon Thomas

Keyword(s):

Integrated Circuits ◽

Process Evaluation ◽

Large Scale ◽

Technology Development ◽

Analytical Techniques ◽

Successful Implementation ◽

Analysis Of Failures ◽

Characterization Of Materials ◽

Circuits Vlsi

Trends in the technology development of very large scale integrated circuits (VLSI) have been in the direction of higher density of components with smaller dimensions. The scaling down of device dimensions has been not only laterally but also in depth. Such efforts in miniaturization bring with them new developments in materials and processing. Successful implementation of these efforts is, to a large extent, dependent on the proper understanding of the material properties, process technologies and reliability issues, through adequate analytical studies. The analytical instrumentation technology has, fortunately, kept pace with the basic requirements of devices with lateral dimensions in the micron/ submicron range and depths of the order of nonometers. Often, newer analytical techniques have emerged or the more conventional techniques have been adapted to meet the more stringent requirements. As such, a variety of analytical techniques are available today to aid an analyst in the efforts of VLSI process evaluation. Generally such analytical efforts are divided into the characterization of materials, evaluation of processing steps and the analysis of failures.

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Scanning Electron Microscopy in Hybrid Microelectronics

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100092244 ◽

1976 ◽

Vol 34 ◽

pp. 456-457

Author(s):

S. Khadpe ◽

R. Faryniak

Keyword(s):

Integrated Circuits ◽

Thick Film ◽

Integrated Circuit ◽

Failure Modes ◽

Three Dimensional ◽

Circuit Components ◽

Hybrid Microcircuit ◽

Electrical Connections ◽

Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

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Electron microscopy study of reactively sputter-deposited Ti/N films on silicon

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100131449 ◽

1992 ◽

Vol 50 (2) ◽

pp. 1362-1363

Author(s):

V. C. Kannan ◽

A. K. Singh ◽

R. B. Irwin ◽

S. Chittipeddi ◽

F. D. Nkansah ◽

...

Keyword(s):

Integrated Circuits ◽

Large Scale ◽

Hexagonal Phase ◽

Microscopy Study ◽

Electron Microscopy Study ◽

Process Conditions ◽

Tin Films ◽

Wide Range ◽

Fcc Phase ◽

Circuits Vlsi

Titanium nitride (TiN) films have historically been used as diffusion barrier between silicon and aluminum, as an adhesion layer for tungsten deposition and as an interconnect material etc. Recently, the role of TiN films as contact barriers in very large scale silicon integrated circuits (VLSI) has been extensively studied. TiN films have resistivities on the order of 20μ Ω-cm which is much lower than that of titanium (nearly 66μ Ω-cm). Deposited TiN films show resistivities which vary from 20 to 100μ Ω-cm depending upon the type of deposition and process conditions. TiNx is known to have a NaCl type crystal structure for a wide range of compositions. Change in color from metallic luster to gold reflects the stabilization of the TiNx (FCC) phase over the close packed Ti(N) hexagonal phase. It was found that TiN (1:1) ideal composition with the FCC (NaCl-type) structure gives the best electrical property.

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The Structure and Properties of MoSi2 Thin Film in Mos Process

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s1431927600001379 ◽

1980 ◽

Vol 38 ◽

pp. 326-327

Author(s):

C.K. Wu ◽

P. Chang ◽

N. Godinho

Keyword(s):

Thin Film ◽

Integrated Circuits ◽

High Performance ◽

Large Scale ◽

Process Development ◽

Structure And Properties ◽

Metal Silicides ◽

High Oxidation ◽

Important Approach ◽

High Oxidation Resistance

Recently, the use of refractory metal silicides as low resistivity, high temperature and high oxidation resistance gate materials in large scale integrated circuits (LSI) has become an important approach in advanced MOS process development (1). This research is a systematic study on the structure and properties of molybdenum silicide thin film and its applicability to high performance LSI fabrication.

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