Three-dimensional thermal analysis of high density triple-level interconnection structures in very large scale integrated circuits

1994 ◽  
Vol 12 (1) ◽  
pp. 59 ◽  
Author(s):  
Xiang Gui
Keyword(s):  
Thermal Analysis ◽  
Integrated Circuits ◽  
Large Scale ◽  
Three Dimensional ◽  
High Density

High-Density Large-Area-Array Interconnects Formed by Low-Temperature Cu/Sn–Cu Bonding for Three-Dimensional Integrated Circuits

2012 ◽  
Vol 59 (7) ◽  
pp. 1941-1947 ◽  
Author(s):  
M. R. Lueck ◽  
J. D. Reed ◽  
C. W. Gregory ◽  
A. Huffman ◽  
J. M. Lannon ◽  
...  
Keyword(s):  
Low Temperature ◽  
Integrated Circuits ◽  
Three Dimensional ◽  
High Density ◽  
Large Area ◽  
Area Array ◽  
Cu Bonding

scholarly journals Layout and Thermal Analysis of Power Devices Using a PC/XC

1990 ◽  
Vol 14 (2) ◽  
pp. 95-109
Author(s):  
J. N. Avaritsiotis ◽  
G. Eleftheriades
Keyword(s):  
Thermal Analysis ◽  
Integrated Circuits ◽  
High Reliability ◽  
Linear Equations ◽  
Single Layer ◽  
High Density ◽  
Computer Work ◽  
Bottom Surface ◽  
Systems Of Linear Equations ◽  
New Treatment

Thermal analysis during the design process is an essential step towards the achievement of high reliability in modern high density hybrid and integrated circuits. Thermal analysis is also essential for modern, high density PCBs. Traditionally, a solution of the thermal problem is obtained by either the method of finite differences or the method of finite elements. Both methods, however, require a fine 3-D partition of the substrate, leading to large systems of linear equations the solution of which demands substantial computing power provided by number crunching machines and/or powerful computer work-stations.The widespread use of personal computers, however, dictates the development of new approaches to the thermal problems so that a design engineer can solve them in reasonable time with a PC. A new treatment of steady-state thermal analysis combined with a layout editor is proposed in this paper, which makes use of the analytical solution for the temperature distribution in a single-layer substrate with heat sources on the surface, and having an isothermal bottom surface. In this way the mathematical complexity of the problem is dramatically reduced allowing the thermal analysis of Multi Chip Modules (M.C.M.s) and complex hybrid circuits with the use of a PC/XT or compatible.

scholarly journals Design and Implementation of a Large Scale Tree-Based QR Decomposition Using a 3D Virtual Systolic Array and a Lightweight Runtime

2014 ◽  
Vol 24 (04) ◽  
pp. 1442004
Author(s):  
Ichitaro Yamazaki ◽  
Jakub Kurzak ◽  
Piotr Luszczek ◽  
Jack Dongarra
Keyword(s):  
Integrated Circuits ◽  
Systolic Array ◽  
Large Scale ◽  
Three Dimensional ◽  
Qr Decomposition ◽  
Dense Matrix ◽  
Von Neumann ◽  
Computing Paradigm ◽  
Array Architecture ◽  
Von Neumann Architecture

A systolic array provides an alternative computing paradigm to the von Neumann architecture. Though its hardware implementation has failed as a paradigm to design integrated circuits in the past, we are now discovering that the systolic array as a software virtualization layer can lead to an extremely scalable execution paradigm. To demonstrate this scalability, in this paper, we design and implement a 3D virtual systolic array to compute a tile QR decomposition of a tall-and-skinny dense matrix. Our implementation is based on a state-of-the-art algorithm that factorizes a panel based on a tree-reduction. Freed from the constraint of a planar layout, we present a three-dimensional virtual systolic array architecture for this algorithm. Using a runtime developed as a part of the Parallel Ultra Light Systolic Array Runtime (PULSAR) project, we demonstrate on a Cray-XT5 machine how our virtual systolic array can be mapped to a large-scale machine and obtain excellent parallel performance. This is an important contribution since such a QR decomposition is used, for example, to compute a least squares solution of an overdetermined system, which arises in many scientific and engineering problems.

A Review of Recent Advances in Thermal Management in Three Dimensional Chip Stacks in Electronic Systems

2011 ◽  
Vol 133 (4) ◽  
Author(s):  
Vikram Venkatadri ◽  
Bahgat Sammakia ◽  
Krishnaswami Srihari ◽  
Daryl Santos
Keyword(s):  
Thermal Analysis ◽  
Integrated Circuits ◽  
Thermal Management ◽  
Management Strategies ◽  
Research Work ◽  
Experimental Studies ◽  
Three Dimensional ◽  
3D Integration ◽  
The Past ◽  
Planar Circuits

Three dimensional (3D) integration offers numerous electrical advantages like shorter interconnection distances between different dies in the stack, reduced signal delay, reduced interconnect power and design flexibilities. The main enabler of 3D integration is through-silicon-vias (TSVs) and stacking of multiple dies. Irrespective of these advantages, thermal management in 3D stacks poses significant challenges for the implementation of 3D integrated circuits. Even though extensive research work has been done in understanding the thermal management in two dimensional (2D) planar circuits for the past several decades, 3D integration offers a new set of challenges in terms of thermal management, which makes it difficult to readily apply the thermal management strategies available for 2D planar circuits. Over the past decade, some work has been done in thermal analysis and management of 3D stacks but still, knowledge is scattered and a comprehensive understanding is lacking. This research work focuses on bringing together the limited work on thermal analysis and thermal management in 3D vertically integrated circuits available in the literature. A compilation and analysis of the results from investigations on thermal management in 3D stacks is presented in this review with special emphasis on experimental studies conducted on different thermal management strategies. Furthermore, 3D integration technologies, thermal management challenges, and advanced 2D thermal management solutions are discussed.

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