An Iterative Computational Technique for Performance Evaluation of Networks-on-Chip

Sahar Foroutan; Yvain Thonnart; Frederic Petrot

doi:10.1109/tc.2012.85

An Iterative Computational Technique for Performance Evaluation of Networks-on-Chip

IEEE Transactions on Computers ◽

10.1109/tc.2012.85 ◽

2013 ◽

Vol 62 (8) ◽

pp. 1641-1655 ◽

Cited By ~ 12

Author(s):

Sahar Foroutan ◽

Yvain Thonnart ◽

Frederic Petrot

Keyword(s):

Performance Evaluation ◽

Computational Technique ◽

Networks On Chip ◽

On Chip

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Floorplan Based Performance Evaluation of 3D Variants of Mesh and BFT Networks-on-Chip

2018 International Conference on Signal Processing and Communications (SPCOM) ◽

10.1109/spcom.2018.8724488 ◽

2018 ◽

Author(s):

Bheemappa Halavar ◽

Basavaraj Talawar

Keyword(s):

Performance Evaluation ◽

Networks On Chip ◽

On Chip

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Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation

IEEE Transactions on Computers ◽

10.1109/tc.2008.142 ◽

2009 ◽

Vol 58 (1) ◽

pp. 32-45 ◽

Cited By ~ 316

Author(s):

Brett Stanley Feero ◽

Partha Pratim Pande

Keyword(s):

Performance Evaluation ◽

Three Dimensional ◽

Networks On Chip ◽

On Chip ◽

A Performance

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Performance evaluation of single- and multi-hop wireless networks-on-chip with NAS Parallel Benchmarks

Journal of the Brazilian Computer Society ◽

10.1186/s13173-015-0027-y ◽

2015 ◽

Vol 21 (1) ◽

Cited By ~ 1

Author(s):

Amanda M.P. Amorim ◽

Poliana A.C. Oliveira ◽

Henrique C. Freitas

Keyword(s):

Wireless Networks ◽

Performance Evaluation ◽

Networks On Chip ◽

On Chip

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Networks-on-Chip Architecture Customization using Network Partitioning: A System-Level Performance Evaluation

International Journal of Computing and Digital Systems ◽

10.12785/ijcds/040103 ◽

2015 ◽

Vol 3 (3) ◽

pp. 19-31

Author(s):

Ahmed A. Morgan, et. al.

Keyword(s):

Performance Evaluation ◽

System Level ◽

Network Partitioning ◽

Networks On Chip ◽

On Chip ◽

Level Performance

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Three-Dimensional Networks-on-Chip: Performance Evaluation

Integrated Circuits and Systems - 3D Integration for NoC-based SoC Architectures ◽

10.1007/978-1-4419-7618-5_6 ◽

2010 ◽

pp. 115-145 ◽

Cited By ~ 1

Author(s):

Brett Stanley Feero ◽

Partha Pratim Pande

Keyword(s):

Performance Evaluation ◽

Three Dimensional ◽

Networks On Chip ◽

On Chip

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A parametric-based performance evaluation and design trade-offs for interconnect architectures using FPGAs for networks-on-chip

Microprocessors and Microsystems ◽

10.1016/j.micpro.2014.04.011 ◽

2014 ◽

Vol 38 (5) ◽

pp. 375-398 ◽

Cited By ~ 8

Author(s):

Sani Abba ◽

Jeong-A Lee

Keyword(s):

Performance Evaluation ◽

Networks On Chip ◽

Trade Offs ◽

Interconnect Architectures ◽

On Chip

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BrownPepper: A SystemC-based simulator for performance evaluation of Networks-on-Chip

2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC) ◽

10.1109/vlsisoc.2009.6041361 ◽

2009 ◽

Cited By ~ 2

Author(s):

Jaison Valmor Bruch ◽

Magnos Roberto Pizzoni ◽

Cesar Albenes Zeferino

Keyword(s):

Performance Evaluation ◽

Networks On Chip ◽

On Chip

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Comparative performance evaluation of latency and link dynamic power consumption modelling algorithms in wormhole switching networks on chip

Journal of Systems Architecture ◽

10.1016/j.sysarc.2016.01.002 ◽

2016 ◽

Vol 63 ◽

pp. 33-47 ◽

Cited By ~ 3

Author(s):

James Harbin ◽

Leandro Soares Indrusiak

Keyword(s):

Performance Evaluation ◽

Power Consumption ◽

Switching Networks ◽

Comparative Performance ◽

Networks On Chip ◽

Dynamic Power ◽

Wormhole Switching ◽

On Chip

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Performance evaluation of wireless networks on chip architectures

2009 10th International Symposium on Quality of Electronic Design ◽

10.1109/isqed.2009.4810319 ◽

2009 ◽

Cited By ~ 11

Author(s):

Amlan Ganguly ◽

Kevin Chang ◽

Partha Pratim Pande ◽

Benjamin Belzer ◽

Alireza Nojeh

Keyword(s):

Wireless Networks ◽

Performance Evaluation ◽

Networks On Chip ◽

On Chip

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An Automated Traffic Generation Framework for Performance Evaluation of Networks-on-Chip for Real World Use Cases

2021 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) ◽

10.1109/ispass51385.2021.00022 ◽

2021 ◽

Author(s):

Sri Harsha Gade ◽

Anup Gangwar ◽

Ambica Prasad ◽

Nitin Kumar Agarwal ◽

Ravishankar Sreedharan

Keyword(s):

Performance Evaluation ◽

Real World ◽

Use Cases ◽

Networks On Chip ◽

Traffic Generation ◽

On Chip

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