Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems

2006 ◽  
Author(s):  
Bertrand Gal ◽  
Caaliph Andriamisaina ◽  
Emmanuel Casseau
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Digital Signal ◽  
High Level Synthesis ◽  
Signal Processing Systems ◽  
High Level

High-Level Synthesis for Real-Time Digital Signal Processing

1993 ◽  
Author(s):  
Jan Vanhoof ◽  
Karl Rompaey ◽  
Ivo Bolsens ◽  
Gert Goossens ◽  
Hugo Man
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Real Time ◽  
Digital Signal ◽  
High Level Synthesis ◽  
High Level

ASIC Design of Natural Frequency of ECG Signal for Atrial Fibrillation Detection Module using High-Level Synthesis Approach

2015 ◽  
Vol 74 (6) ◽  
Author(s):  
Nurul Ashikin Abdul-Kadir ◽  
Norlaili Mat Safri ◽  
Mohd Afzan Othman
Keyword(s):  
Atrial Fibrillation ◽  
Signal Processing ◽  
Feature Extraction ◽  
Digital Signal Processing ◽  
Natural Frequency ◽  
Synthesis Method ◽  
Digital Signal ◽  
High Level Synthesis ◽  
Ecg Signal ◽  
High Level

The growth of interest in the development of reduced-scale electrocardiogram (ECG) system based on field-programmable gated-array (FPGA) design platform is increasing. This study provides initial result of mapping digital signal processing to hardware design for specific purpose. In this paper, a part of digital signal processing for atrial fibrillation classification was implemented to register-transfer level (RTL) design. The specific part was feature extraction of ECG signal. The algorithm of ECG signal feature extraction was natural frequency from second-order system for detecting atrial fibrillation. By applying high-level synthesis method, three designs were implemented for natural frequency behavior. The designs were two Single-Cycle (Design 1 and Design 2) and Multi-Cycle fully-constraint (Design 3), of which logic utilization consist of 2530, 36 and 1, respectively. Performance evaluation among all designs were compared.

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