Combined word-length optimization and high-level synthesis of digital signal processing systems

2001 ◽  
Vol 20 (8) ◽  
pp. 921-930 ◽  
Author(s):  
Ki-Il Kum ◽  
Wonyong Sung
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Word Length ◽  
Digital Signal ◽  
High Level Synthesis ◽  
Signal Processing Systems ◽  
High Level ◽  
Length Optimization

scholarly journals High-Level Synthesis under Fixed-Point Accuracy Constraint

2012 ◽  
Vol 2012 ◽  
pp. 1-14 ◽  
Author(s):  
Daniel Menard ◽  
Nicolas Herve ◽  
Olivier Sentieys ◽  
Hai-Nam Nguyen
Keyword(s):  
Signal Processing ◽  
Fixed Point ◽  
Word Length ◽  
High Level Synthesis ◽  
Floating Point ◽  
Fixed Point Arithmetic ◽  
Resource Binding ◽  
High Level ◽  
Point Arithmetic ◽  
Length Optimization

Implementing signal processing applications in embedded systems generally requires the use of fixed-point arithmetic. The main problem slowing down the hardware implementation flow is the lack of high-level development tools to target these architectures from algorithmic specification language using floating-point data types. In this paper, a new method to automatically implement a floating-point algorithm into an FPGA or an ASIC using fixed-point arithmetic is proposed. An iterative process on high-level synthesis and data word-length optimization is used to improve both of these dependent processes. Indeed, high-level synthesis requires operator word-length knowledge to correctly execute its allocation, scheduling, and resource binding steps. Moreover, the word-length optimization requires resource binding and scheduling information to correctly group operations. To dramatically reduce the optimization time compared to fixed-point simulation-based methods, the accuracy evaluation is done through an analytical method. Different experiments on signal processing algorithms are presented to show the efficiency of the proposed method. Compared to classical methods, the average architecture area reduction is between 10% and 28%.

High-Level Synthesis for Real-Time Digital Signal Processing

1993 ◽  
Author(s):  
Jan Vanhoof ◽  
Karl Rompaey ◽  
Ivo Bolsens ◽  
Gert Goossens ◽  
Hugo Man
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Real Time ◽  
Digital Signal ◽  
High Level Synthesis ◽  
High Level

ASIC Design of Natural Frequency of ECG Signal for Atrial Fibrillation Detection Module using High-Level Synthesis Approach

2015 ◽  
Vol 74 (6) ◽  
Author(s):  
Nurul Ashikin Abdul-Kadir ◽  
Norlaili Mat Safri ◽  
Mohd Afzan Othman
Keyword(s):  
Atrial Fibrillation ◽  
Signal Processing ◽  
Feature Extraction ◽  
Digital Signal Processing ◽  
Natural Frequency ◽  
Synthesis Method ◽  
Digital Signal ◽  
High Level Synthesis ◽  
Ecg Signal ◽  
High Level

The growth of interest in the development of reduced-scale electrocardiogram (ECG) system based on field-programmable gated-array (FPGA) design platform is increasing. This study provides initial result of mapping digital signal processing to hardware design for specific purpose. In this paper, a part of digital signal processing for atrial fibrillation classification was implemented to register-transfer level (RTL) design. The specific part was feature extraction of ECG signal. The algorithm of ECG signal feature extraction was natural frequency from second-order system for detecting atrial fibrillation. By applying high-level synthesis method, three designs were implemented for natural frequency behavior. The designs were two Single-Cycle (Design 1 and Design 2) and Multi-Cycle fully-constraint (Design 3), of which logic utilization consist of 2530, 36 and 1, respectively. Performance evaluation among all designs were compared.

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