Design of an optically differential reconfigurable gate array VLSI chip with optically and electrically controlled logic blocks

2004 ◽  
Author(s):  
M. Watanabe ◽  
F. Kobayashi
Keyword(s):  
Vlsi Chip ◽  
Gate Array ◽  
Logic Blocks

scholarly journals A BIST Methodology to test CLB Resources on an SRAM-Based FPGA using Complementary Gates Configuration

2020 ◽  
Vol 9 (12) ◽  
pp. 217-220
Keyword(s):  
Field Programmable Gate Array ◽  
Test Pattern ◽  
Fault Coverage ◽  
Area Overhead ◽  
Field Programmable ◽  
Self Test ◽  
Gate Array ◽  
Built In Self Test ◽  
Pattern Generators ◽  
Logic Blocks

This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA). The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs. No extra area overhead is needed to accommodate the test pattern generators (TPGs) and output responses analyzers (ORAs) as they are realized by the already existing configurable resources on the FPGA.A group of CLBs chosen as block under test (BUT) are configured as complementary gates (AND/NAND, OR/NOR, XOR/XNOR) to successfully test the aforementioned faults. The proposed BIST structure when implemented on Xilinx Virtex-4 FPGA proved 100% fault coverage and minimized test configurations.

Heat Diffusion in an Optical Logic Gate Array on Silicon-on-Sapphire

1997 ◽  
Vol 7 (3) ◽  
pp. 739-748
Author(s):  
H. Gualous ◽  
A. Koster ◽  
D. Pascal ◽  
S. Laval
Keyword(s):  
Logic Gate ◽  
Heat Diffusion ◽  
Optical Logic ◽  
Optical Logic Gate ◽  
Gate Array

A New High-Density 10T CMOS Gate-Array Base Cell for Two-Port SRAM Applications

2016 ◽  
Vol E99.C (6) ◽  
pp. 717-726
Author(s):  
Nobutaro SHIBATA ◽  
Yoshinori GOTOH ◽  
Takako ISHIHARA
Keyword(s):  
High Density ◽  
Gate Array
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