Thick-Gate-Oxide MOS Structures with Sub-Design-Rule (SDR) Polysilicon Lengths for RF Circuit Applications

2008 ◽  
Author(s):  
Haifeng Xu ◽  
Kenneth K. O
Keyword(s):  
Gate Oxide ◽  
Design Rule ◽  
Mos Structures ◽  
Rf Circuit

Tunneling Effects in NH3 Annealed 4H-SiC Trench MOSFETs

2020 ◽  
Vol 1004 ◽  
pp. 652-658
Author(s):  
Judith Berens ◽  
Gregor Pobegen ◽  
Tibor Grasser
Keyword(s):  
Effective Activation Energy ◽  
Charge Trapping ◽  
Gate Oxide ◽  
Device Performance ◽  
Trap Level ◽  
Effective Activation ◽  
Oxide Reliability ◽  
Trap Assisted Tunneling ◽  
Assisted Tunneling ◽  
Mos Structures

The interface between the gate oxide and silicon carbide (SiC) has a strong influence on the performance and reliability of SiC MOSFETs and thus, requires special attention. In order to reduce charge trapping at the interface, post oxidation anneals (POAs) are conventionally applied. However, these anneals do not only influence the device performance, such as mobility and on-resistance, but also the gate oxide reliability. We study the oxide tunneling mechanisms of NH3 annealed 4H-SiC trench MOSFET test structures and compare them to devices which received a NO POA. We show that 3 different mechanisms, namely trap assisted tunneling (TAT), Fowler-Nordheim (FN) tunneling and charge trapping are found for NH3 annealed MOS structures whereas only FN-tunneling is observed in NO annealed devices.The tunneling barrier suggest a trap level with an effective activation energy of 382 meV to enable TAT.

Effect of Phosphorus-Doped Polysilicon Anneal on Thin Oxide Reliability as Probed with X-Ray Damage Characterization

1994 ◽  
Vol 338 ◽  
Author(s):  
R. Nachman ◽  
F. Cerrina
Keyword(s):  
Gate Oxide ◽  
Radiation Sensitivity ◽  
Oxide Charge ◽  
X Ray ◽  
Damage Characterization ◽  
Oxide Reliability ◽  
The Creation ◽  
Thin Oxide ◽  
Phosphorus Doped ◽  
Mos Structures

ABSTRACTIn this paper we address the degradation of oxide reliability after annealing the phosphorusdoped polysilicon of MOS structures. The oxide reliability was studied in terms of X-ray radiation sensitivity as well as breakdown characteristics.We found that annealing the polysilicon increased the radiation sensitivity of the gate oxide. We believe that this increase is a result of the phosphorus out-diffusion from the polysilicon into the oxide and a result of the creation of phosphorus related traps in the oxide bulk. We also found that the oxide charge to breakdown (Qbd) degradation correlates well with the density of the phosphorus in the oxide.

Impact of Post-Trench Processing on the Electrical Characteristics of 4H-SiC Trench-MOS Structures with Thick Top and Bottom Oxides

2015 ◽  
Vol 821-823 ◽  
pp. 753-756 ◽  
Author(s):  
Christian T. Banzhaf ◽  
Michael Grieb ◽  
Martin Rambach ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Inert Gas ◽  
Breakdown Field ◽  
Wafer Surface ◽  
Mos Devices ◽  
Uniform Current ◽  
Thin Gate Oxide ◽  
Mos Structures

This study focuses on the evaluation of different post-trench processes (PTPs) for Trench-MOSFETs. Thereto, two different types of inert gas anneals at process temperatures above 1250 °C are compared to a sacrificial oxidation as PTP. The fabricated 4H-SiC Trench-MOS structures feature a thick silicon dioxide (SiO2) both at the wafer surface (‘top’) and in the bottom of the trenches (‘bottom’) in order to characterize only the thin gate oxide at the trenched sidewalls. It is shown that an inert gas anneal at a process temperature between 1400 °C and 1550 °C yields uniform current/electric field strength (IE) values and excellent dielectric breakdown field strengths up to 12 MV/cm using a SiO2 gate oxide of approximately 40 nm thickness. Charge-to-breakdown (QBD) measurements at a temperature T of 200 °C confirm the necessity of a high temperature inert gas anneal after 4H-SiC trench etching in order to fabricate reliable Trench-MOS devices. QBD values up to 16.2 C/cm² have been measured at trenched and high temperature annealed sidewalls, which is about twice the measured maximum QBD value of the corresponding planar reference MOS structure. The capacitive MOS interface characterization points out the need for a sacrificial oxidation subsequent to a high temperature inert gas anneal in order to ensure a high quality MOS interface with excellent electrical properties.

Electrical Properties of MOS Structures on 4H-SiC (11-20) Face

2013 ◽  
Vol 740-742 ◽  
pp. 621-624 ◽  
Author(s):  
Junji Senzaki ◽  
Atsushi Shimozato ◽  
Kozutoshi Kajima ◽  
Keiko Aryoshi ◽  
Takahito Kojima ◽  
...  
Keyword(s):  
Nitrous Oxide ◽  
Harmful Effect ◽  
Gate Oxide ◽  
The Other ◽  
Oxide Semiconductor ◽  
Power Devices ◽  
Channel Mobility ◽  
Oxide Reliability ◽  
Dry Oxidation ◽  
Mos Structures

Threshold voltage (VTH) instability, channel mobility and oxide reliability have been investigated for meta-oxide-semiconductor (MOS) structures on 4H-SiC (11-20) face using various gate oxidation procedures. Channel mobility of n-channel MOSFET with a gate oxide by pyrogenic oxidation is higher than that by dilute-DRY oxidation followed by a nitrous oxide (N2O) post-oxidation annealing (POA). On the other hand, oxide reliability for the pyrogenic oxides is poor compared with the dilute-DRY/N2O oxides. A Hydrogen POA is effective in an improvement of channel mobility for both oxides, but causes a harmful effect on VTH stability. Temperature dependence of VTH instability indicates that MOS structure grown by dilute-DRY followed by N2O POA is suitable for a practical use of SiC MOS power devices.

Challenges of High-Performance and High-Reliablity in SiC MOS Structures

2012 ◽  
Vol 717-720 ◽  
pp. 703-708 ◽  
Author(s):  
Junji Senzaki ◽  
Atsushi Shimozato ◽  
Kazutoshi Kojima ◽  
Tomohisa Kato ◽  
Yasunori Tanaka ◽  
...  
Keyword(s):  
Epitaxial Layer ◽  
High Performance ◽  
Surface Defects ◽  
Gate Oxide ◽  
Fabrication Process ◽  
Power Devices ◽  
Effective Technique ◽  
Gate Oxides ◽  
Related Defect ◽  
Mos Structures

Influences of wafer-related defect and gate oxide fabrication process on MOS characteristics with gate oxides thermally grown on 4H-SiC (0001) wafer have been investigated for a realization of SiC MOS power devices. The SiC MOS characteristics depend on the gate oxide fabrication process, and are improved by the increase of DRY oxidation temperature and the applying of N2O and H2 POAs. In addition, it was clearly shown that predominant origins of SiC MOS reliability degradation are wafer-related defects such as dislocation and surface defects of epitaxial layer. Moreover, the planarization of SiC epitaxial layer surface using a CMP treatment is effective technique for the improvement of SiC MOS reliability.

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