Memory efficient column-layered decoder design for non-binary LDPC codes

2012 ◽  
Author(s):  
Kai He ◽  
Jin Sha ◽  
Zhongfeng Wang
Keyword(s):  
Ldpc Codes ◽  
Efficient Column ◽  
Decoder Design ◽  
Memory Efficient

Memory-Efficient Sum–Product Decoding of LDPC Codes

2004 ◽  
Vol 52 (8) ◽  
pp. 1225-1230 ◽  
Author(s):  
H. Sankar ◽  
K.R. Narayanan
Keyword(s):  
Ldpc Codes ◽  
Memory Efficient

scholarly journals High Throughput and Resource Efficient Pipelined Decoder Designs for Projective Geometry LDPC Codes

2019 ◽  
Vol 64 (2) ◽  
pp. 179-191
Author(s):  
Ved Mitra ◽  
Mahesh C. Govil ◽  
Girdhari Singh ◽  
Sanjeev Agrawal
Keyword(s):  
Projective Geometry ◽  
Critical Path ◽  
Ldpc Codes ◽  
Cmos Technology ◽  
Quantization Scheme ◽  
Path Delay ◽  
Bit Rate ◽  
Error Performance ◽  
Ldpc Decoder ◽  
Decoder Design

Projective geometry (PG) based low-density parity-check (LDPC) decoder design using iterative sum-product decoding algorithm (SPA) is a big challenge due to higher interconnection and computational complexity, and larger memory requirement caused by relatively higher node degrees. PG-LDPC codes using SPA exhibits the best error performance and faster convergence. This paper presents an efficient novel decoding method, modified SPA (MSPA) that not only shortens the critical-path delay but also improves the hardware utilization and throughput of the decoder while maintaining the error performance of SPA. Three fully-parallel LDPC decoder designs based on PG structure, PG(2,GF( 2s )) of LDPC codes are introduced. These designs differ in their bit-node (BN) and check-node (CN) architectures. Fixed-point, 9-bit quantization scheme is used to achieve better error performance. Another significant contribution of this work is the pipelining of the proposed decoder architectures to further enhance the overall throughput. These parallel and pipelined designs are implemented for 73-bit (rate 0.616) and 1057-bit (rate 0.769) regular-structured PG-LDPC codes, on Xilinx Virtex-6 LX760 FPGA and on 0.18 μm CMOS technology for ASIC. Synthesis and simulation results have shown the better performance, throughput and effectiveness of the proposed designs.

Memory Efficient Decoder Architectures for Quasi-Cyclic LDPC Codes

2008 ◽  
Vol 55 (9) ◽  
pp. 2898-2911 ◽  
Author(s):  
Yongmei Dai ◽  
Ning Chen ◽  
Zhiyuan Yan
Keyword(s):  
Ldpc Codes ◽  
Memory Efficient
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