A simulation study of the bit interference effects in an ultra-thin-body, double-gate, trapped-charge-storage type non-volatile memory cell

2008 ◽  
Author(s):  
Wen-Jer Tsai ◽  
T.F. Ou ◽  
J.S. Huang ◽  
T.C. Lu ◽  
K.C. Chen ◽  
...  
Keyword(s):  
Simulation Study ◽  
Memory Cell ◽  
Thin Body ◽  
Charge Storage ◽  
Double Gate ◽  
Interference Effects ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
Storage Type ◽  
Trapped Charge

Quantum Dot Gate (QDG) Quantum Dot Channel (QDC) Multistate Logic Non-Volatile Memory (NVM) with High-K Dielectric HfO2 Barriers

2020 ◽  
Vol 29 (01n04) ◽  
pp. 2040001
Author(s):  
N. R. Butterfield ◽  
R. Mays ◽  
B. Khan ◽  
R. Gudlavalleti ◽  
F. C. Jain
Keyword(s):  
Quantum Dot ◽  
Hafnium Oxide ◽  
Experimental Testing ◽  
Memory Cell ◽  
Floating Gate ◽  
Carrier Injection ◽  
High K ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
High K Dielectric

This paper presents the theory, fabrication and experimental testing results for a multiple state Non-Volatile Memory (NVM), comprised of hafnium oxide high-k dielectric tunnel and gate barriers as well as a Silicon Quantum Dot Superlattice (QDSL) implemented for the floating gate and inversion channel (QDG) and (QDC) respectively. With the conclusion of Moore’s Law for conventional transistor fabrication, regarding the minimum gate size, current efforts in memory cell research and development are focused on bridging the gap between the conventions of the past sixty years and the future of computing. One method of continuing the increasing chip density is to create multistate devices capable of storing and processing additional logic states beyond 1 and 0. Replacing the silicon nitride floating gate of a conventional Flash NVM with QDSL gives rise to minibands that result in greater control over charge levels stored in the QDG and additional intermediate states. Utilizing Hot Carrier Injection (HCI) programming, for the realized device, various magnitudes of gate voltage pulses demonstrated the ability to accurately control the charge levels stored in the QDG. This corresponds to multiple threshold voltage shifts allowing detection of multiple states during read operations.

A Novel Trapping-Nitride-Storage Non-Volatile Memory Cell Using a Gated-Diode Structure With an Ultra-Thin Dielectric Dopant Diffusion Barrier

2008 ◽  
Vol 55 (8) ◽  
pp. 2202-2211
Author(s):  
Wen-Jer Tsai ◽  
Tien-Fan Ou ◽  
Hsuan-Ling Kao ◽  
Erh-Kun Lai ◽  
Jyun-Siang Huang ◽  
...  
Keyword(s):  
Diffusion Barrier ◽  
Memory Cell ◽  
Diode Structure ◽  
Dopant Diffusion ◽  
Non Volatile Memory ◽  
Volatile Memory

MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET

2022 ◽  
Vol 27 (2) ◽  
pp. 1-18
Author(s):  
Shaahin Angizi ◽  
Navid Khoshavi ◽  
Andrew Marshall ◽  
Peter Dowben ◽  
Deliang Fan
Keyword(s):  
High Speed ◽  
Memory Cell ◽  
Low Power Design ◽  
Evaluation Framework ◽  
Cache Memory ◽  
Array Architecture ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
Memory Applications ◽  
First Time

Magneto-Electric FET ( MEFET ) is a recently developed post-CMOS FET, which offers intriguing characteristics for high-speed and low-power design in both logic and memory applications. In this article, we present MeF-RAM , a non-volatile cache memory design based on 2-Transistor-1-MEFET ( 2T1M ) memory bit-cell with separate read and write paths. We show that with proper co-design across MEFET device, memory cell circuit, and array architecture, MeF-RAM is a promising candidate for fast non-volatile memory ( NVM ). To evaluate its cache performance in the memory system, we, for the first time, build a device-to-architecture cross-layer evaluation framework to quantitatively analyze and benchmark the MeF-RAM design with other memory technologies, including both volatile memory (i.e., SRAM, eDRAM) and other popular non-volatile emerging memory (i.e., ReRAM, STT-MRAM, and SOT-MRAM). The experiment results for the PARSEC benchmark suite indicate that, as an L2 cache memory, MeF-RAM reduces Energy Area Latency ( EAT ) product on average by ~98% and ~70% compared with typical 6T-SRAM and 2T1R SOT-MRAM counterparts, respectively.

A new multitime programmable non-volatile memory cell using high voltage NMOS

2018 ◽  
Vol 88-90 ◽  
pp. 169-172
Author(s):  
S. Xu ◽  
H. Wang ◽  
J. Wu ◽  
L. Zheng ◽  
J. Diao
Keyword(s):  
High Voltage ◽  
Memory Cell ◽  
Non Volatile Memory ◽  
Volatile Memory
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